Pequeno (meaning "tiny" in Spanish) aka PQR5 is a 5-staged pipelined in-order RISC-V CPU Core compliant with RV32I ISA. The core is bare RTL designed in System Verilog, balanced for area/performance, and portable across platforms like FPGA, ASIC.
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RV32I ISA v2.2
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Single-core, Single-issue, In-order execution
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Classic 5-stage RISC-V pipeline
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Intended for baremetal embedded applications, not OS & interrupt capable.
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| CPU Feature Set | |
|---|---|
| ISA | RV32I, user-level v2.2 |
| Instructions | All 37 base instructions |
| Cores | 1 |
| Issue | One instruction per cycle |
| Pipeline depth | 5 |
| Fetch, Decode, Execution, Memory Access, Writeback | |
| Execution model | In-order |
| Bus architecture | Harvard, separate instruction/data bus |
| Branch prediction | Yes, static |
| Cache | Not available, but can be integrated externally |
| OS capable | No, privilege modes are not supported |
| Interrupt/Exceptions capable | No |
| Parameter / Macro | |
|---|---|
| RF_IN_BRAM | Maps Register File to Block RAM instead of LUT RAM/Flops |
| PC_INIT | Reset PC vector |
This RV32I assembler supports all 37 base instructions + 16 pseudo instructions
Assembler and Instruction Manual: https://github.com/iammituraj/pqr5asm
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FPGA demo video of Pequeno running Hello world!
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FPGA demo video of Pequeno being flashed by peqFlash through serial interface (UART) and running Blinky LED program
The validation was done on Xilinx Artix-7 based FPGA boards Basys-3, CMOD-A735T
| Synthesis summary | |
|---|---|
| Core version | v1.1_beta |
| Configuration | Register File in LUT RAMs |
| Target | Artix-7, xc7a35tcpg236-1 |
| LUTs | 1060 |
| Registers | 551 |
| Max clock freq | 115 MHz |
| Max clock freq in fastest Artix-7 speed grade | 165 MHz |
| Performance Validation | |
|---|---|
| Core version | v1.1_beta |
| CoreMark score | 0.75 CoreMark/MHz |
| Iterations | 400 |
| Iterations per second | 9 |
| Test clock freq | 12 MHz |
| Test platform | FPGA |
| Full Report | coremark/coremark_report.html |
Follow the journey of Pequeno in my blog, how this RISC-V CPU was designed in RTL from scratch: pequeno blogs in chipmunklogic.com
Please go through readme_database for complete info about this repo database and how to setup the PQR5 build environment.
This CPU core is intended for educational purposes only. The users must review the accompanying license document (LICENSE) for detailed terms and conditions before the use.
Mitu Raj, Chipmunk Logic, chip@chipmunklogic.com