Starred repositories
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
A bot that accepts PDF docs and lets you ask questions on it.
This textbook gives students an understanding of the most important topics in embedded systems design using a coherent, compelling and hands-on approach.
Design and program Arm-based embedded systems and implement them in low-level hardware using standard C and assembly language.
Design and program Arm-based embedded systems and implement them using commercial API
A textbook on introduction to Digital Signal Processing fundamentals
Master programming by recreating your favorite technologies from scratch.
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
Software for the IO-Link Master Shield/Hat for Arduino and Raspberry Pi
Linux Driver for USB WiFi Adapters that are based on the RTL8812BU and RTL8822BU Chipsets - v5.13.1
pathogen.vim: manage your runtimepath
Edit SystemVerilog files (and UVM files) in Vim/gVim
🌊 Digital timing diagram rendering engine
Generate address space documentation HTML from compiled SystemRDL input
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
An icon taskbar for the Gnome Shell. This extension moves the dash into the gnome main panel so that the application launchers and system tray are combined into a single panel, similar to that foun…
🎓 Path to a free self-taught education in Computer Science!
Cheatsheets for web development - devhints.io
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!