Digital Design Engineer @ Texas Instruments
< 57E1 svg class="octicon octicon-link" viewBox="0 0 16 16" version="1.1" width="16" height="16" aria-hidden="true">Mail : kavinxraj@gmail.com
- Computer Architecture
- RISC V
- SoC Design
- Digital circuit Design, RTL Design
- Micro Architecture
- System Verilog, Verilog
- Synthesis, Equivalence Checking
- Basics of UPF and SDC
- Low Power Design
- Static Timing Analysis
- RTL-to-GDS flow
- FPGA Implementation
- Documentation
- Perl / Python / Tcl Scripting
- Bash/Csh Linux Shell
- Finite State Machine Design
- Execution Plannnig
- Computer Architecture
- Computer Hardware
- Simulation
- vcs
- xcelium
- Synthesis
- fusion compiler
- genus
- Static Checks ( Lint | CDC )
- spyglass
- jaspergold
- Equivalence Checking
- conformal
- Physical Design
- innovus
- virtuoso
- Timing
- tempus
- FPGA
- xilinx vivado
- General
- git
- vim