8000 MMU: H-Mode PTW permission and TLB fix by NicolasDerumigny · Pull Request #2933 · openhwgroup/cva6 · GitHub
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MMU: H-Mode PTW permission and TLB fix #2933

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MMU: H-Mode PTW permission and TLB fix #2933

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5afb128
fix(cva6_mmu): fix hgatp translation of stores
NicolasDerumigny Apr 9, 2025
fcf59be
refactor+fix(MMU): fix wrong htval value from TLB in guest PF
NicolasDerumigny Apr 13, 2025
8fd5e3b
fix(ptw): do not throw an execption on G-intermediate translation of …
NicolasDerumigny Apr 15, 2025
641caf9
lint(cva6_mmu): fix coding 8000 style
NicolasDerumigny Apr 15, 2025
838780a
lint(ptx): check verible on tlb, mmu and ptw
NicolasDerumigny Apr 16, 2025
5bef70e
Merge branch 'master' into dev/nderumig/fix-mmu
JeanRochCoulon May 15, 2025
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22 changes: 11 additions & 11 deletions core/cva6_mmu/cva6_mmu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,6 @@ module cva6_mmu
output dcache_req_i_t req_port_o,

// PMP

input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i,
input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i
);
Expand Down Expand Up @@ -400,16 +399,15 @@ module cva6_mmu
};

if (CVA6Cfg.PtLevels == 3 && itlb_is_page[CVA6Cfg.PtLevels-2]) begin

// Strange 9+PtLevels to avoid CI errors on (purely syntactic) checks on Sv32, where
// `PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)` equals `11` and would lead to `icache_areq_i.fetch_vaddr[11:12]`
icache_areq_o.fetch_paddr[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels] = icache_areq_i.fetch_vaddr[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels];

end

if (itlb_is_page[0]) begin

icache_areq_o.fetch_paddr[PPNWMin:12] = icache_areq_i.fetch_vaddr[PPNWMin:12];

end

// ---------//
// ITLB Hit
// --------//
Expand Down Expand Up @@ -453,7 +451,7 @@ module cva6_mmu
if (CVA6Cfg.TvalEn) icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(update_vaddr);
if (CVA6Cfg.RVH) begin
icache_areq_o.fetch_exception.tval2 = ptw_bad_gpaddr[CVA6Cfg.GPLEN-1:0];
icache_areq_o.fetch_exception.tinst=(ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0);
icache_areq_o.fetch_exception.tinst = (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0);
icache_areq_o.fetch_exception.gva = v_i;
end
end else begin
Expand Down Expand Up @@ -544,13 +542,15 @@ module cva6_mmu
if ((en_ld_st_translation_i || en_ld_st_g_translation_i) && !misaligned_ex_q.valid) begin
lsu_valid_o = 1'b0;

lsu_dtlb_ppn_o = (en_ld_st_g_translation_i && CVA6Cfg.RVH)? dtlb_g_content.ppn :dtlb_content.ppn;
lsu_dtlb_ppn_o = (en_ld_st_g_translation_i && CVA6Cfg.RVH)?dtlb_g_content.ppn:dtlb_content.ppn;
lsu_paddr_o = {
(en_ld_st_g_translation_i && CVA6Cfg.RVH) ? dtlb_gpte_q.ppn : dtlb_pte_q.ppn,
lsu_vaddr_q[11:0]
};

if (CVA6Cfg.PtLevels == 3 && dtlb_is_page_q[CVA6Cfg.PtLevels-2]) begin
// Strange 9+PtLevels to avoid CI errors on (purely syntactic) checks on Sv32, where
// `PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)` equals `11` and would lead to `lsu_paddr_o[11:12]`
lsu_paddr_o[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels] = lsu_vaddr_q[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels];
lsu_dtlb_ppn_o[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels] = lsu_vaddr_n[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels];
end
Expand Down Expand Up @@ -584,7 +584,7 @@ module cva6_mmu
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
};
if (CVA6Cfg.RVH) begin
lsu_exception_o.tval2= CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]);
lsu_exception_o.tval2 = CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]);
lsu_exception_o.tinst = '0;
lsu_exception_o.gva = ld_st_v_i;
end
Expand All @@ -611,7 +611,7 @@ module cva6_mmu
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
};
if (CVA6Cfg.RVH) begin
lsu_exception_o.tval2= CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]);
lsu_exception_o.tval2 = CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]);
lsu_exception_o.tinst = '0;
lsu_exception_o.gva = ld_st_v_i;
end
Expand Down Expand Up @@ -652,7 +652,7 @@ module cva6_mmu
};
if (CVA6Cfg.RVH) begin
lsu_exception_o.tval2 = ptw_bad_gpaddr[CVA6Cfg.GPLEN-1:0];
lsu_exception_o.tinst= (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0);
lsu_exception_o.tinst = (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0);
lsu_exception_o.gva = ld_st_v_i;
end
end else begin
Expand All @@ -678,7 +678,7 @@ module cva6_mmu
};
if (CVA6Cfg.RVH) begin
lsu_exception_o.tval2 = ptw_bad_gpaddr[CVA6Cfg.GPLEN-1:0];
lsu_exception_o.tinst= (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0);
lsu_exception_o.tinst = (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0);
lsu_exception_o.gva = ld_st_v_i;
end
end else begin
Expand Down
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