8000 Added syntax highlighting for the Verilog and VHDL languages by aballet · Pull Request #5641 · outline/outline · GitHub
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Added syntax highlighting for the Verilog and VHDL languages 8000 #5641

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Merged
merged 2 commits into from
Aug 4, 2023
Merged

Added syntax highlighting for the Verilog and VHDL languages #5641

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1fbce53
Added syntax highlighting for the Verilog and VHDL languages
aballet Aug 2, 2023
ea884fa
Revert unwanted changes in CodeFence.ts
aballet Aug 2, 2023
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2 changes: 2 additions & 0 deletions shared/editor/extensions/Prism.ts
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Expand Up @@ -47,6 +47,8 @@ export const LANGUAGES = {
tsx: "TSX",
typescript: "TypeScript",
vb: "Visual Basic",
verilog: "Verilog",
vhdl: "VHDL",
yaml: "YAML",
zig: "Zig",
};
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4 changes: 4 additions & 0 deletions shared/editor/nodes/CodeFence.ts
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Expand Up @@ -48,6 +48,8 @@ import swift from "refractor/lang/swift";
import toml from "refractor/lang/toml";
import tsx from "refractor/lang/tsx";
import typescript from "refractor/lang/typescript";
import verilog from "refractor/lang/verilog";
import vhdl from "refractor/lang/vhdl";
import visualbasic from "refractor/lang/visual-basic";
import yaml from "refractor/lang/yaml";
import zig from "refractor/lang/zig";
Expand Down Expand Up @@ -113,6 +115,8 @@ const DEFAULT_LANGUAGE = "javascript";
toml,
typescript,
tsx,
verilog,
vhdl,
visualbasic,
yaml,
zig,
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0