8000 Added syntax highlighting for the Verilog and VHDL languages by aballet · Pull Request #5641 · outline/outline · GitHub
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Added syntax highlighting for the Verilog and VHDL languages #5641

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Merged
merged 2 commits into from
Aug 4, 2023
Merged

Added syntax highlighting for the Verilog and VHDL languages #5641

merged 2 commits into from
Aug 4, 2023

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aballet
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@aballet aballet commented Aug 2, 2023

Adds the following languages to Outline's syntax highlighting:

  • Verilog
  • VHDL

@auto-assign auto-assign bot requested a review from tommoor 8000 August 2, 2023 10:25
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CLAassistant commented Aug 2, 2023 •
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@tommoor tommoor merged commit 16f1328 into outline:main Aug 4, 2023
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@tommoor tommoor tommoor approved these changes

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