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29 Open 67 Closed
29 Open 67 Closed
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Issues list

Xyce CMake build system should not install admsXml
#144 opened May 17, 2025 by tvrusso
question about pulse sources and convergence
#143 opened May 14, 2025 by olisnr
Model Not Found Error for FinFET Inverter Simulation in Xyce 7.8
#140 opened Apr 8, 2025 by gowreddysuresh
3
Error in level 2 diode VJ and CJ0 calculations?
#138 opened Mar 31, 2025 by smindinvern
9
how to debug .ac and .step?
#135 opened Feb 27, 2025 by olisnr
3
PWL bridges for mixed signal (co-simulation)
#133 opened Feb 6, 2025 by kev-cam
@Karlsefni2012
3
Transient noise support by extra noisy models
#131 opened Jan 28, 2025 by EngGhaith
1
Xyce does not recognize the model card correctly on Ubuntu
#130 opened Jan 19, 2025 by jiaxinmax
2
Error in Qucs (Version 0.0.19)Transmission Line Simulation using Smith Chart and its comparison with CST Schematic Simulation
#120 opened Dec 2, 2024 by DrIngAmin
1
.ac documentations strange: order of parameters should {step} {init} {final} and 100MEG-steps are a bit sensless...
#119 opened Nov 26, 2024 by olisnr
2
sp simulation using touchstone file
#116 opened Nov 17, 2024 by caglarozdag
1
Xyce 7.7.0 compilation fails unless -D Trilinos_ENABLE_Epetra=ON is set when building Trilinos
#111 opened Oct 28, 2024 by dolphingarlic
2
Compilation fails
#107 opened Aug 19, 2024 by KrzysztofHerman
1
build requires deprecated trilinos packages
#102 opened Jul 17, 2024 by Kreijstal
4
Error while installing trilinos for xyce
#101 opened Jul 2, 2024 by gowreddysuresh
1
Build error on Ubuntu 20.04 LTS
#100 opened Jun 17, 2024 by chenshih1
11
Is there a plan for RHEL 8 support?
#99 opened Apr 25, 2024 by jaemyeongKim
HB analysis: different result on Windows and Linux
#93 opened Dec 25, 2023 by jsmith173
Release Notes: RHEL 7 is certified-supported while any Linux distro other than RHEL 6 is build-supported
#92 opened Dec 15, 2023 by omasanori
Build error on Ubuntu 22.04.3 LTS
#91 opened Aug 27, 2023 by leihaoda
1
CV 6C85 S output of noise analysis
#89 opened Jun 1, 2023 by arpadbuermen
1
Xyce/ADMS: Verilog-A system task inconsistencies
#74 opened Sep 12, 2022 by ngwood
2
Transcient simulation error
#71 opened Aug 16, 2022 by laurentc2
5
some model parameter should be integer but ...
#66 opened Jul 1, 2022 by laurentc2
2
Add ability to parameterize transient end time
#59 opened Apr 4, 2022 by olde-fortran
3
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