Stars
preliminary for Teknofest Digital Processor Contest
ROS package to find a rigid-body transformation between a LiDAR and a camera for "LiDAR-Camera Calibration using 3D-3D Point correspondences"
EtherCard is an IPv4 driver for the ENC28J60 chip, compatible with Arduino IDE
Beti Elektronik - ddApp -10 FPGA Uygulamaları (Eğitim) Seti
Have you decided to learn the Python language or want to repeat the basic concepts? Then this repo is for you.
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)
A 32 bits Microcontroller based on RISC-V RV32I ISA
Hardware designs modelled with verilog
Single-cycle MIPS processor in Verilog HDL.
Verilog description of the Risc-V processor
A 32-bit ALU using combinational logic written in Verilog.
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
A 32-bit Kogge-Stone Adder is implemented in this design.