10000 JiteshNayak2004 (JiteshNayak2004) / Repositories · GitHub
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  • capstone Public

    collection of all codes resources scripts and docs i made for my btech capstone project

    C Updated May 14, 2025
  • dotfiles Public

    dotfiles recovery

    Lua Updated May 11, 2025
  • JLLVM Public

    Forked from llvm/llvm-project

    The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

    LLVM Other Updated Apr 30, 2025
  • vluespec Public

    bluespec learning repository

    Updated Mar 18, 2025
  • cachesim Public

    implementing a direct mapped write through cache simulator

    C++ Updated Mar 3, 2025
  • Flame thrower is a on-chip network router written in bluespec system verilog

    Bluespec Updated Feb 9, 2025
  • Jerilator Public

    Forked from mjeje/verilator

    Verilator open-source SystemVerilog simulator and lint system

    C++ GNU Lesser General Public License v3.0 Updated Feb 4, 2025
  • C Updated Nov 12, 2024
  • single cycle risc-v core implementation

    SystemVerilog Updated Sep 19, 2024
  • JUART Public

    uart protocol implementation in systemverilog

    SystemVerilog 2 Updated Sep 17, 2024
  • HLS Public

    compilation of learnings on HLS from various resources via vitis

    SystemVerilog Updated Sep 5, 2024
  • COD-Lab Public

    Forked from alfadelta10010/COD-Lab

    Instructions & Assignments for COD Lab - UE22EC352A

    Assembly Updated Sep 5, 2024
  • raytracer Public

    implementing a simple raytracer in cpp

    C++ Updated Aug 17, 2024
  • git-trial Public

    test for r5 lab

    Updated Aug 5, 2024
  • Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

    C++ Apache License 2.0 Updated Jul 23, 2024
  • contains simple basic block implementation in various hdl's

    SystemVerilog Updated Jul 7, 2024
  • JFPU Public

    floating point unit following the IEEE 754 standard

    SystemVerilog Updated Jun 17, 2024
  • Detecting real time violence using computer vision and ml

    Jupyter Notebook 1 Updated Jun 4, 2024
  • ML_LAB Public

    Jupyter Notebook Updated Apr 15, 2024
  • personal website

    SCSS Updated Mar 31, 2024
  • lab files for arm soc design course

    Verilog Updated Mar 25, 2024
  • agrisaathi Public

    Python 1 Updated Mar 14, 2024
  • predicting router position by analyzing wlan throughput

    C++ 1 2 Updated Mar 14, 2024
  • deep-detect Public

    a deepfake detector usign the cnn and lstm architecture

    Jupyter Notebook 2 Updated Mar 14, 2024
  • PD_ASIC Public

    this is a repo that contains the notes and lab assignments for physical design for ASIC course

    Verilog Updated Feb 16, 2024
  • Verilog Updated Feb 12, 2024
  • Config files for my GitHub profile.

    Updated Feb 7, 2024
  • a file transfer cli to share files b/w two devices using socket programming

    Python 1 Updated Feb 2, 2024
  • SystemVerilog Tutorial

    SystemVerilog GNU General Public License v3.0 Updated Nov 29, 2023
  • grc files for gnu radio used in the silent room hackathon

    Python Updated Nov 2, 2023
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