Re-Cache: Mitigating cache contention by exploiting locality characteristics with reconfigurable memory hierarchy for GPGPUs
Modern GPGPUs have employed multi-threading to hide the long off-chip memory access latency caused by frequent cache misses. However, the limited cache capacity shared by thousands of concurrently running warps will introduce serious ...
A Reconfigurable 8-to-10-bit 20-to-5-GS/s time-interleaved time-domain ADC
This paper presents a 16-way time-interleaved (TI) time-domain (TD) analog-to-digital converter (ADC) with full multiplexing of hardware resources and highly synchronous reconfigurable from 8-to-10-bit 20-to-5-GS/s accuracy and speed ...
Complexity reduction in multilevel speculative DFEs with unconstrained receiver response
An approach to timing recovery and adaptation that significantly lowers the complexity multilevel wireline receiver is presented in this article. The approach consists of the utilization of the data slicers intended for speculative ...
Improvement of cell internal weak defects detection under process variation by optimizing test path and test pattern
Advances in integrated circuit process technology have led to new defect mechanisms, and weak resistive defects in standard cells have received attention in addition to traditional defect types. Such defects are categorized as small ...
Cost effective Tanh activation function circuits based on fast piecewise linear logic
In this paper, an approximate 16-bit non-linear Tanh function circuit design is proposed for activation function in neural networks and digital signal processing, which is based on piecewise linear calculation. By sacrificing ...
A level shifter for high-side GaN drivers with enhanced dV/dt immunity and speed
—In this paper, a level shifter with high dV/dt immunity and high speed is presented for GaN drivers. During dV/dt transitions of floating power supply, a resistor-based decoupling technique (RDT) is applied for the level shifter to ...
Miniaturized silicon-based substrate integrated waveguide filter for 6G applications
Based on Through-Silicon Via (TSV) technology, a Substrate Integrated Waveguide (SIW) bandpass filter with ultra-compact size is presented for sixth-generation (6G) mobile communication applications. The proposed filter is proposed by ...
A low jitter fractional PLL with offset current charge pump
A low jitter fractional phase-locked loop (PLL) with high quality local oscillator signal for RF transceiver is presented in this paper. Compared with the traditional structure, not only the gated-offset linearization technique is ...
Effect of lateral straggle parameter on Hetero Junction Dual Gate Vertical TFET
In this Article, the effects of lateral straggle parameter variation and Temperature variation have been investigated on Hetero Junction Dual Gate Vertical TFET. Although the TFET is a viable alternative to the MOSFET, the performance ...
The effect of silicon films impurity compensation on the performance of silicon drift detector
Silicon drift detector (SDD) fabricated using in-situ doping technology has been developed in recent years since its advantages of low process temperature and ultra-shallow junction. However, the N+ and P+ regions on the same substrate ...
Ge/Si interfaced label free nanowire BIOFET for biomolecules detection - analytical analysis
This paper comprehensively investigates a dielectric modulated Ge/Si interfaced label free nanowire BIOFET for biomolecules detection. The main highlight of this work is the structural novelty in nanowire BIOFET which is integrated ...
0.18-μm CMOS process 40 MHz–4.41 GHz frequency synthesizer with high linearity low phase noise varactor-reconstruction LC-VCO
A 40 MHz–4.41 GHz fractional-N frequency synthesizer (FS) with varactor-reconstruction VCO (VRVCO) fabricated in the standard 0.18-μm CMOS process is demonstrated. In the conventional VCO, owing to non-linearity of varactor and ...
Investigation of switching and inverter characteristics of Recessed-Source/Drain (Re–S/D) Silicon-on-Insulator (SOI) Feedback Field Effect Transistor (FBFET)
In this paper, the switching and inverter characteristics of Recessed-Source/Drain (Re–S/D) Silicon-on-Insulator (SOI) Feedback Field Effect Transistor (FBFET) are presented using a TCAD mixed-mode simulator. FBFETs have recently ...
Comparative study of Negative Capacitance Field Effect Transistors with different doped hafnium oxides
Negative Capacitance Field Effect Transistors are well known for their superior performance over MOSFET and are a viable candidate to succeed the baseline FET in time ahead. We have studied the performance of 32 nm planar MOSFET with ...
A 24-kHz BW 90.5-dB SNDR 96-dB DR continuous-time delta-sigma modulator using FIR DAC feedback
This paper presents a single bit continuous time delta-sigma modulator (CTDSM) with finite impulse response (FIR) feedback DAC designed for audio applications. By using FIR feedback in the input stage, the linearity requirements of the ...
Multi-dimensional accumulation gate LDMOS with ultra-low specific on-resistance
A novel multi-dimensional accumulation gate (MDAG) lateral double-diffused MOS (LDMOS) with ultra-low specific on-resistance (R on,sp) is proposed and investigated by simulation. The MDAG LDMOS is composed of the MDAG, ...
Potential and electric field analysis of field plated AlGaN/GaN HEMT for high voltage applications using 2-D analytical approach
A physics-based 2-D analytical model is developed for field plated AlGaN/GaN high electron mobility transistor (HEMT) and the effect of field plate on potential and electric field is analyzed. The complete generalized theory developed ...
On the SRAM with comb-shaped nano FETs advancing to 3 nm node and beyond
In this paper, we describe several scaling challenges of SRAM consisting of FinFETs and horizontal Gate-All-Around (GAA) Nano-sheet Field-Effect-Transistors (NshFETs), especially investigations related to Design-Technology Co-...
Systematic characterization for RF small-signal parameter extraction of 28 nm FDSOI MOSFETs up to 110 GHz
A systematic RF characterization and small-signal parameter extraction for 28 nm fully depleted silicon on insulator (FDSOI) MOSFETs is presented in this paper. Two-step and hybrid de-embedding methodologies have been applied and ...
Refined simulation method and failure study of BGA package structure based on image drive
The packaging structure, internal defects, and external loads have a significant impact on the reliability and ultimate failure of chip performance. Therefore, establishing a refined model that considers multiple factors is of great ...
A 6.435-nW, 26.2-ppm/°C hybrid bandgap reference with stacked ΔVGS compensation in sub-threshold region
This paper illustrates a methodology to design an ultra-low power hybrid bandgap reference (HBR) with high accuracy to counteract the effect of temperature using single BJT and MOSFETs working in subthreshold region. Based on ...
Investigation of variable field plate length in GaN HEMT on SiC substrate for MMIC applications
This work intends to improve the GaN HEMT device breakdown voltage, by uniformly distributing peak electric field using field plate engineering technique. A peak electric field reduction is observed by adding field plate at the gate ...
A fully integrated ultra-low noise low-dropout regulator inherently combined with bandgap reference for SoC applications
This paper presents a capacitor-less ultra-low noise low-dropout regulator (LDO) inherently combined with bandgap reference (BGR). Compared to traditional LDOs with a dedicated error amplifier (EA) followed by a BGR to generate a ...