IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Emerging 4G wireless communication systems need to deliver much higher data rates, more flexibility, and a significantly higher energy efficiency than current systems. To cope with this immense increase of requirements, new design approaches are a ...

Large area/delay/power overheads are required to support the reconfigurability of field-programmable gate arrays (FPGAs). We proposed a hybrid CMOS/nanotechnology dynamically reconfigurable architecture, called NATURE, earlier to address this challenge. ...

In this paper, a hybrid 1-bit full adder design employing both complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was ...

A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst case input rate. However, due to their rigid structure, they ...

In this paper, a data-jitter mixing (DJM) forwarded-clock receiver is proposed that achieves high jitter correlation between data and a clock for high speed and small power consumption. The first-stage injection-locked oscillator (ILO) filters out high-...

As memory density continues to grow in modern systems, accurate analysis of static RAM (SRAM) stability is increasingly important to ensure high yields. Traditional static noise margin metrics fail to capture the dynamic characteristics of SRAM behavior, ...

Network-on-chip based many-core processors break the limitations faced with single-core processors, and can bring high performance, improved yield, and high reliability. They are widely considered as the most promising platform. One of the most important ...

This paper comprises two new methodologies to improve yield and reduce system-on-a-chip power. The first methodology is based on faulty static random-access memory (SRAM) cells detections and cache resizing. The key advantage of this approach is that it ...

Back-end wearout mechanisms are major reliability concerns for modern microprocessors. In this paper, a framework that contains modules for back-end time-dependent dielectric breakdown, electromigration, and stress-induced voiding is proposed to analyze ...

A 3-D test circuit examining thermal propagation within a through-silicon via-based 3-D integrated stack has been designed, fabricated, and tested. Design insight into thermal coupling in 3-D integrated circuits (ICs) through both experiment and ...

We present linear and nonlinear techniques for design exploration of an iterative algorithm. The nonlinear techniques allow control of processor workload and control of communication between processors. The algorithm considered is the Sunar-Koç ...

As we advance into the era of nanotechnology, semiconductor devices are scaled down to their physical limits, thereby opening up venues for new transistor channel materials based on nanowires and nanotubes. Transistors based on nanowires and nanotubes ...

In this paper, we propose a mapping algorithm called particle filter mapping (PFMAP); PFMAP is able to map task nodes onto the cores of tile-based network-on-chip (NoC) architectures, such as regular, irregular, and custom 2-D or 3-D topologies. PFMAP is ...

In this paper, n-tier methodology is developed to design multilevel interconnect architecture of macrocells using single-wall carbon nanotube (SWCNT) bundles. Upper limit of low-bias voltage of SWCNT bundle interconnects is derived and its dependence on ...

Asymmetry in read/write access latencies, which leads to issues of blocking writes and low throughput performance, is a common challenge impeding the integration of emerging nonvolatile memory technologies into high-performance computing systems. ...

In recent years, nonvolatile memory (NVM) technologies, such as spin-transfer torque random-access memory (RAM) (STT-RAM) and phase change RAM, have drawn a lot of attention due to their low leakage and high density. However, both of these NVMs suffer ...

This paper explores efficient memory management schemes for memory-based architectures of the fast Fourier transform (FFT). A data relocation scheme that merges multiple banks to lower the area requirement and power dissipation of memory-based FFT ...

The combination of software flexibility and hardware configurability makes partially reconfigurable application-specific instruction-set processor (rASIP) an attractive architecture, which matches the needs of computation-intensive and fast-evolving ...

In this paper, we investigate the opportunity brought by controllable-polarity transistors to design efficient reconfigurable circuits. Controllable-polarity transistors are devices whose polarity can be electrostatically programmed to be either n- or p-...

Video-based navigation (VBN) is increasingly used in space applications to enable autonomous entry, descent, and landing of aircrafts. VBN algorithms require real-time performances and high computational capabilities, especially to perform features ...

In this paper, we present a novel architecture based on field-programmable gate arrays (FPGAs) for the reconstruction of compressively sensed signal using the orthogonal matching pursuit (OMP) algorithm. We have analyzed the computational complexities and ...

Support vector machines (SVM) are a popular class of supervised models in machine learning. The associated compute intensive learning algorithm limits their use in real-time applications. This paper presents a fully scalable architecture of a coprocessor, ...

In the post-CMOS scenario a primary role is played by the quantum-dot cellular automata (QCA) technology. Irrespective of the specific implementation principle (e.g., either molecular, or magnetic or semiconductive in the current scenario) the intrinsic ...

Passivity enforcement is an important issue for macromodeling for passive systems from measured or simulated data. Existing passivity enforcement techniques based on iteratively fixing the passivity either suffer from convergence issue or lack optimality ...

To increase the quality of wireless transmission, wireless communication systems employ advanced forward error correction codes such as turbo codes and low-density parity-check (LDPC) codes. To achieve smooth transition between turbo and LDPC decoding in ...

Polar codes, as the first provable capacity-achieving error-correcting codes, have received much attention in recent years. However, the decoding performance of polar codes with traditional successive-cancellation (SC) algorithm cannot match that of the ...

In this paper, depth map estimation circuit design based on structured light is proposed, wherein a projection light source and an image sensor are utilized in combination to achieve a depth map estimation chip, an accurate, low complex circuit is ...

This paper presents a multicore and multichannel (MCMC) technology and a synchronous and forward-backward scheduling (SFBS) for the cost reduction of sequential minimal optimization trainable pattern classifier. The MCMC technology uses multiple ...

As different tiers are stacked together in 3-D integrated circuits, the power/ground (P/G) network simulation becomes more challenging than that of 2-D cases. In this brief, we propose a hierarchical simulation method suitable for 3-D P/G network (HS3-DPG)...

An 8th-order fully electronically programmable complex filter based on current amplifiers for multistandard mobile TV applications is presented. Its center frequency, pole frequency, and gain are electronically programmable to accommodate both Integrated ...