Tsin-Yuan Chang

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Mingjun Hsiao (7)
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Yuanho Chen (3)
Chihwen Lu (2)
Chin-Long Wey (2)
Chung-Yi Li (2)
PoLin Chen (2)
Shao-Shen Yang (2)
Shao-Sheng Yang (2)
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Journal/Magazine Names

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (5)
IEEE Design & Test (2)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2)
IEEE Transactions on Circuits and Systems II: Express Briefs (1)

Proceedings/Book Names

ATS '02: Proceedings of the 11th Asian Test Symposium (2)
ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference (1)
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference (1)
ATS '00: Proceedings of the 9th Asian Test Symposium (1)
ATS '01: Proceedings of the 10th Asian Test Symposium (1)
ATS '04: Proceedings of the 13th Asian Test Symposium (1)
ATS '06: Proceedings of the 15th Asian Test Symposium (1)
DAC '88: Proceedings of the 25th ACM/IEEE Design Automation Conference (1)
DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference (1)
Design of fault-tolerant programmable logic arrays for yield enhancement (1)
ICETCE '12: Proceedings of the 2012 Second International Conference on Electric Technology and Civil Engineering (1)
ITC '01: Proceedings of the 2001 IEEE International Test Conference (1)
Proceedings of the IEEE International Test Conference 2001 (1)

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Proceedings (13)
Other periodicals (10)
Doctoral Theses (1)

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IEEE Computer Society (9)
IEEE Educational Activities Department (5)
IEEE Press (4)
IEEE Computer Society Press (3)
Association for Computing Machinery (2)
Michigan State University (1)

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research-article
High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic
- Yuan-Ho Chen
  Department of Information and Computer Engineering, Chung Yuan Christian University, Zhongli, Taiwan
  ,
- Jyun-Neng Chen
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
  ,
- Tsin-Yuan Chang
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
  ,
- Chih-Wen Lu
  Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 22, Issue 3•March 2014, pp 463-474 • https://doi.org/10.1109/TVLSI.2013.2251021

This paper proposes a low-cost high-throughput multistandard transform (MST) core, which can support MPEG-1/2/4 (8$\,\times\,$8), H.264 (8$\,\times\,$8, 4 $\,\times\,$4), and VC-1 (8$\,\times\,$8, 8$\,\times\,$4, 4 $\,\times\,$8, 4$\,\times\,$4) ...
2Citation
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High Accuracy Fixed-width Booth Multipliers with Probabilistic Estimation Compensated Method
ICETCE '12: Proceedings of the 2012 Second International Conference on Electric Technology and Civil Engineering•May 2012, pp 1460-1463

In this research, a probabilistic estimation compensation (PEC) method for fixed-width Booth multiplier is proposed. According to the probabilistic analysis for the truncation part, a formula is obtained to calculate the compensation value easily. In ...
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A high performance video transform engine by using space-time scheduling strategy
- Yuan-Ho Chen
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
  ,
- Tsin-Yuan Chang
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 20, Issue 4•April 2012, pp 655-664 • https://doi.org/10.1109/TVLSI.2011.2110620

In this paper, a spatial and time scheduling strategy, called the space-time scheduling (STS) strategy, that achieves high image resolutions in real-time systems is proposed. The proposed spatial scheduling strategy includes the ability to choose the ...
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Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG
- Chung-Yi Li
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
  ,
- Yuan-Ho Chen
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
  ,
- Tsin-Yuan Chang
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
  ,
- Lih-Yuan Deng
  Department of Mathematical Sciences, The University of Memphis, Memphis, U. S. A.
  ,
- Kiwing To
  Institute of Physics, Academia Sinica, Taipei, Taiwan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 20, Issue 2•February 2012, pp 385-389 • https://doi.org/10.1109/TVLSI.2010.2103332

We present a new reseeding-mixing method to extend the system period length and to enhance the statistical properties of a chaos-based logistic map pseudo random number generator (PRNG). The reseeding method removes the short periods of the digitized ...
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High throughput DA-based DCT with high accuracy error-compensated adder tree
- Yuan-Ho Chen
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
  ,
- Tsin-Yuan Chang
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
  ,
- Chung-Yi Li
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19, Issue 4•April 2011, pp 709-714 • https://doi.org/10.1109/TVLSI.2009.2037968

In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the ...
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Fast test integration: toward plug-and-play at-speed testing of multiple clock domains based on IEEE standard 1500
- Po-Lin Chen
  Department of Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan
  ,
- Yu-Chieh Huang
  Department of Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan
  ,
- Tsin-Yuan Chang
  Department of Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 29, Issue 11•November 2010, pp 1837-1842 • https://doi.org/10.1109/TCAD.2010.2055010

The rapid advance of semiconductor technology exposes multifrequency designs to severe reliability loss due to incomplete at-speed testing, which is induced by ignorance of timing-related defects between clocks. However, the reduced testability caused by ...
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A 2.4-GS/s FFT processor for OFDM-based WPAN applications
- Song-Nien Tang
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
  ,
- Jui-Wei Tsai
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
  ,
- Tsin-Yuan Chang
  Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 57, Issue 6•June 2010, pp 451-455 • https://doi.org/10.1109/TCSII.2010.2048373

This brief presents a fast Fourier transform (FFT) processor that provides high throughput rate (T.R.) by applying the eight-data-path pipelined approach for wireless personal area network applications. The hardware costs, including the power ...
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IEEE standard 1500 compatible delay test framework
- Po-Lin Chen
  Department of Electrical Engineering, National Tsing-Hua University, HsinChu, Taiwan
  ,
- Jhih-Wei Lin
  Department of Electrical Engineering, National Tsing-Hua University, HsinChu, Taiwan
  ,
- Tsin-Yuan Chang
  Department of Electrical Engineering, National Tsing-Hua University, HsinChu, Taiwan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 17, Issue 8•August 2009, pp 1152-1156 • https://doi.org/10.1109/TVLSI.2009.2013983

Rapid advances in semi-conductor technology have made timing-related defects increasingly crucial in core-based system-on-chip designs. Currently, modular test strategies based on IEEE Standard 1500 are applied to test the functionality of each embedded ...
1Citation
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A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range
- Chung-Yi Li
  National Tsing Hua University
  ,
- Chia-Yuan Chou
  National Tsing Hua University
  ,
- Tsin-Yuan Chang
  National Tsing Hua University
ATS '06: Proceedings of the 15th Asian Test Symposium•November 2006, pp 313-317

The abstract is to be in fully-justified italicized text, at the top of the left-hand column as it is here, below the author information. Use the word "Abstract" as the title, in 12-point Times, boldface type, centered relative to the column, initially ...
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An efficient output phase assignment for PLA minimization
- C. -L. Wey
  Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI
  ,
- T. -Y. Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 9, Issue 1•November 2006, pp 1-7 • https://doi.org/10.1109/43.45851

When a multiple-output function is realized by a PLA (programmable logic array), there is often the option of realizing either true or complementary logic for each output. The tradeoffs in implementing PLAs with and without output phase assignment are ...
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On-chip accumulated jitter measurement for phase-locked loops
- Chih-Feng Li
  National Tsing-Hua University, Hsinchu, Taiwan
  ,
- Shao-Sheng Yang
  National Tsing-Hua University, Hsinchu, Taiwan
  ,
- Tsin-Yuan Chang
  National Tsing-Hua University, Hsinchu, Taiwan
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference•January 2005, pp 1184-1187• https://doi.org/10.1145/1120725.1120936

A time-to-digital Converter (TDC) circuit is presented to measure the worst-case accumulated jitters over N periods of clock produced by the PLL. Including the most positive jitter and the most negative jitter, the worst case jitters can be calculated ...
1Citation
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Article
A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier
- Yi-Ming Sheng
  National Tsing Hua University
  ,
- Ming-Jun Hsiao
  National Tsing Hua University
  ,
- Tsin-Yuan Chang
  National Tsing Hua University
ATS '04: Proceedings of the 13th Asian Test Symposium•November 2004, pp 272-276• https://doi.org/10.1109/ATS.2004.9

The voltage difference on bit line pairs is a critical parameter while designing Static Random Access Memory (SRAM). In this paper, measurement unit is presented for sampling and amplifying the weak signals of bit line pairs to higher voltage ...
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A Built-In Parametric Timing Measurement Unit
- Ming-Jun Hsiao
  National Tsing Hua University
  ,
- Jing-Reng Huang
  National Tsing Hua University
  ,
- Tsin-Yuan Chang
  National Tsing Hua University
IEEE Design & Test, Volume 21, Issue 4•July 2004, pp 322-330 • https://doi.org/10.1109/MDT.2004.22

On-chip timing-measurement units are needed because accessibility to internal nodes in SoCs is very limited, and performing time interval measurements using automatic test equipment is very difficult and expensive. This article presents a parametric ...
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Timing measurement unit with multi-stage TVC for embedded memories
- Kae-Jiun Mo
  National Tsing-Hua University, Hsinchu, Taiwan
  ,
- Shao-Sheng Yang
  National Tsing-Hua University, Hsinchu, Taiwan
  ,
- Tsin-Yuan Chang
  National Tsing-Hua University, Hsinchu, Taiwan
ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference•January 2004, pp 565-566

To find the maximum access time for embedded memories, a wide range and scalable time-to-digital converter (TDC) composed of multi-stage time-to-voltage converter (TVC), peak voltage detector, voltage-to-time converter (VTC) and ring counter is present. ...
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An Access Timing Measurement Unit of Embedded Memory
ATS '02: Proceedings of the 11th Asian Test Symposium•November 2002, pp 104

As the deep sub-micron techniques evolving,embedded memories are dominating the yield, while thetesting and measurement issues are more difficult due toaccess limitations. To solve the testing problem,BIST circuits are developed for testing the ...
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An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters
ATS '02: Proceedings of the 11th Asian Test Symposium•November 2002, pp 266

In this paper, an embedded built-in-self-test approachfor analog-to-digital converters (ADCs) is presented.This architecture can test the parameters of ADC, whichincludes the differential nonlinearity (DNL) error, integralnonlinearity (INL) error, ...
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An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters
ATS '01: Proceedings of the 10th Asian Test Symposium•November 2001, pp 423

Without a large number of precision reference voltages and with the consideration of matching problems, a built-in-self-test approach is proposed to test the parameters of digital-to-analog converter (DAC), which includes offset error (VOSE,gain error (...
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A BUILT-IN TIMING PARAMETRIC MEASUREMENT UNIT
ITC '01: Proceedings of the 2001 IEEE International Test Conference•October 2001, pp 315

A built-in parametric measurement circuit is proposed for time-interval measurement and setup/hold timemeasurement.The main idea is based on the dual-slopetechnique.The minimum resolution is set by resistorarray configuration,which is 1/16 clock period ...
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A built-in timing parametric measurement unit
Proceedings of the IEEE International Test Conference 2001•October 2001, pp 315-322
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A realistic fault model for flash memories
ATS '00: Proceedings of the 9th Asian Test Symposium•December 2000, pp 274

To explore all faulty behavior on NAND-type flash memory is impractical, and the defects in the SPICE model level are considered. In this paper, two SPICE models of the flash cell are developed and used for circuit-level faulty behavior simulation. The ...
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Q. How do authors access ACM Author-Izer?
A. See How to Use

Q. Why can’t I find my most recent publication in my ACM Author Profile Page?
A. There is a time delay between publication and the process which associates that publication with an Author Profile Page. Right now, that process usually takes 4-8 weeks.

Q. How does ACM Author-Izer expand ACM’s “Green Path” Access Policies?
A. ACM Author-Izer extends the rights and permissions that authors retain even after copyright transfer to ACM, which has been among the “greenest” publishers. ACM enables its author community to retain a wide range of rights related to copyright and reuse of materials. They include:
- Posting rights that ensure free access to their work outside the ACM Digital Library and print publications
- Rights to reuse any portion of their work in new works that they may create
- Copyright to artistic images in ACM’s graphics-oriented publications that authors may want to exploit in commercial contexts
- All patent rights, which remain with the original owner

Tsin-Yuan Chang

Tsin-Yuan Chang

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High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic

High Accuracy Fixed-width Booth Multipliers with Probabilistic Estimation Compensated Method

A high performance video transform engine by using space-time scheduling strategy

Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG

High throughput DA-based DCT with high accuracy error-compensated adder tree

Fast test integration: toward plug-and-play at-speed testing of multiple clock domains based on IEEE standard 1500

A 2.4-GS/s FFT processor for OFDM-based WPAN applications

IEEE standard 1500 compatible delay test framework

A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range

An efficient output phase assignment for PLA minimization

On-chip accumulated jitter measurement for phase-locked loops

A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier

A Built-In Parametric Timing Measurement Unit

Timing measurement unit with multi-stage TVC for embedded memories

An Access Timing Measurement Unit of Embedded Memory

An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters

An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters

A BUILT-IN TIMING PARAMETRIC MEASUREMENT UNIT

A built-in timing parametric measurement unit

A realistic fault model for flash memories