research-article

Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG

Authors:

Kiwing ToAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 20, Issue 2

Pages 385 - 389

https://doi.org/10.1109/TVLSI.2010.2103332

Published: 01 February 2012 Publication History

Abstract

We present a new reseeding-mixing method to extend the system period length and to enhance the statistical properties of a chaos-based logistic map pseudo random number generator (PRNG). The reseeding method removes the short periods of the digitized logistic map and the mixing method extends the system period length to $2^{253}$ by “xoring” with a DX generator. When implemented in the TSMC 0.18- $\mu{\hbox {m}}$ 1P6M CMOS process, the new reseeding-mixing PRNG (RM-PRNG) attains the best throughput rate of 6.4 Gb/s compared with other nonlinear PRNGs. In addition, the generated random sequences pass the NIST SP 800-22 statistical tests including ratio test and U-value test.

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Paul PSadia MHossain MMuldrey BHasan MChen YZhirnov VSasan ASavidis I(2021)Design of a Low-Overhead Random Number Generator Using CMOS-based Cascaded Chaotic MapsProceedings of the 2021 Great Lakes Symposium on VLSI10.1145/3453688.3461504(109-114)Online publication date: 22-Jun-2021
https://dl.acm.org/doi/10.1145/3453688.3461504
Wu YLiu L(2020)An Iteration-Time Combination Method to Reduce the Dynamic Degradation of Digital Chaotic MapsComplexity10.1155/2020/57079832020Online publication date: 1-Jan-2020
https://dl.acm.org/doi/10.1155/2020/5707983
Alawida MSamsudin AAlshoura W(2019)Enhancing One-Dimensional Chaotic Map Based on Bitstream Dividing ModelProceedings of the 2019 8th International Conference on Software and Computer Applications10.1145/3316615.3316657(130-134)Online publication date: 19-Feb-2019
https://dl.acm.org/doi/10.1145/3316615.3316657
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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 20, Issue 2

February 2012

198 pages

ISSN:1063-8210

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IEEE Educational Activities Department

United States

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Published: 01 February 2012

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Paul PSadia MHossain MMuldrey BHasan MChen YZhirnov VSasan ASavidis I(2021)Design of a Low-Overhead Random Number Generator Using CMOS-based Cascaded Chaotic MapsProceedings of the 2021 Great Lakes Symposium on VLSI10.1145/3453688.3461504(109-114)Online publication date: 22-Jun-2021
https://dl.acm.org/doi/10.1145/3453688.3461504
Wu YLiu L(2020)An Iteration-Time Combination Method to Reduce the Dynamic Degradation of Digital Chaotic MapsComplexity10.1155/2020/57079832020Online publication date: 1-Jan-2020
https://dl.acm.org/doi/10.1155/2020/5707983
Alawida MSamsudin AAlshoura W(2019)Enhancing One-Dimensional Chaotic Map Based on Bitstream Dividing ModelProceedings of the 2019 8th International Conference on Software and Computer Applications10.1145/3316615.3316657(130-134)Online publication date: 19-Feb-2019
https://dl.acm.org/doi/10.1145/3316615.3316657
Tang JYu ZLiu L(2019)A delay coupling method to reduce the dynamical degradation of digital chaotic maps and its application for image encryptionMultimedia Tools and Applications10.1007/s11042-019-7602-878:17(24765-24788)Online publication date: 1-Sep-2019
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Bonny TAl Debsi RMajzoub SElwakil A(2019)Hardware Optimized FPGA Implementations of High-Speed True Random Bit Generators Based on Switching-Type Chaotic OscillatorsCircuits, Systems, and Signal Processing10.1007/s00034-018-0905-638:3(1342-1359)Online publication date: 1-Mar-2019
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Michaels A(2018)Improved RNS-based PRNGsProceedings of the 13th International Conference on Availability, Reliability and Security10.1145/3230833.3232806(1-5)Online publication date: 27-Aug-2018
https://dl.acm.org/doi/10.1145/3230833.3232806
Deng LShiau JLu HBowman D(2018)Secure and Fast Encryption (SAFE) with Classical Random Number GeneratorsACM Transactions on Mathematical Software10.1145/321267344:4(1-17)Online publication date: 14-Jul-2018
https://dl.acm.org/doi/10.1145/3212673
Liu LMiao S(2017)Delay-introducing method to improve the dynamical degradation of a digital chaotic mapInformation Sciences: an International Journal10.1016/j.ins.2017.02.031396:C(1-13)Online publication date: 1-Aug-2017
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(2015)A general hybrid model for chaos robust synchronization and degradation reductionInformation Sciences: an International Journal10.1016/j.ins.2015.01.028305:C(146-164)Online publication date: 1-Jun-2015
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Mansingka AAffan Zidan MBarakat MRadwan ASalama K(2013)Fully digital jerk-based chaotic oscillators for high throughput pseudo-random number generators up to 8.77Gbits/sMicroelectronics Journal10.1016/j.mejo.2013.06.00744:9(744-752)Online publication date: 1-Sep-2013
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