- General Chair:
- Mark Franklin,
- Program Chairs:
- D. K. Panda,
- Dimitri Stiliadis
On behalf of the program committee we are both pleased to welcome you to the fourth edition of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS) being held in San Jose, CA.
ANCS has become one of the premier research conferences in networking, and is dedicated to the design of the hardware and software components used to create communication networks. This year, we continued the effort to maintain a high-quality program by addressing the most important research areas. The program includes several papers in areas such as multi-core processors and hardware implementations as they apply to network systems, while also addressing topics in switches, routers, packet classification and network I/O components.
We were fortunate to have an outstanding program committee of 32 members who graciously contributed their time and expertise towards the success of the conference. Every one of them was dedicated and thoroughly reviewed the papers they were assigned, and we are sure the authors will be greatly helped by the feedback provided in the reviews. The quality of any conference is derived from the quality of the submitted papers and the quality of the paper selection process. This conference is indebted to all authors who submitted their best work and to the program committee made of experts in the field.
We received 67 submissions from all over the world. About 60% of the submitted papers were from the U.S. and Canada, about 23% from Asia/Pacific, and about 17% from Europe, Middle East and Africa. Qualified papers received at least three reviews mostly from program committee members. The review process was "double-blind". Authors' identities were kept anonymous throughout the process.
At the end the program committee accepted 17 papers which will be presented in a single track over the two days of the conference. We also chose seven papers from the submitted papers to be presented as posters, with an associated two page abstract that is included in the Proceedings. The program will also have two excellent Keynote Talks and a Panel. We hope that all of you will find the program enjoyable, stimulating and useful to your research, for this would be the best reward for all the work that went into its preparation.
Implementing an OpenFlow switch on the NetFPGA platform
We describe the implementation of an OpenFlow Switch on the NetFPGA platform. OpenFlow is a way to deploy experimental or new protocols in networks that carry production traffic. An OpenFlow network consists of simple flow-based switches in the datapath,...
Design of a scalable network programming framework
Nearly all programmable commercial hardware solutions offered for high-speed networking systems are capable of meeting the performance and flexibility requirements of equipment vendors. However, the primary obstacle to adoption lies with the software ...
A remotely accessible network processor-based router for network experimentation
- Charlie Wiseman,
- Jonathan Turner,
- Michela Becchi,
- Patrick Crowley,
- John DeHart,
- Mart Haitjema,
- Shakir James,
- Fred Kuhns,
- Jing Lu,
- Jyoti Parwatikar,
- Ritun Patney,
- Michael Wilson,
- Ken Wong,
- David Zar
Over the last decade, programmable Network Processors (NPs) have become widely used in Internet routers and other network components. NPs enable rapid development of complex packet processing functions as well as rapid response to changing requirements. ...
Compact architecture for high-throughput regular expression matching on FPGA
In this paper we present a novel architecture for high-speed and high-capacity regular expression matching (REM) on FPGA. The proposed REM architecture, based on nondeterministic finite automaton (RE-NFA), efficiently constructs regular expression ...
Acceleration of decision tree searching for IP traffic classification
Traffic classification remains a hot research problem, especially when facing new traffic trends and new hardware architectures. We propose a classification tree search method called explicit range search, motivated by the characteristics of machine ...
Efficient regular expression evaluation: theory to practice
Several algorithms and techniques have been proposed recently to accelerate regular expression matching and enable deep packet inspection at line rate. This work aims to provide a comprehensive practical evaluation of existing techniques, extending them ...
A scalable multithreaded L7-filter design for multi-core servers
L7-filter is a significant component in Linux's QoS framework that classifies network traffic based on application layer data. It enables subsequent distribution of network resources in respect to the priority of applications. Considerable research has ...
On runtime management in multi-core packet processing systems
Computer networks require increasingly complex packet processing in the data path to adapt to new functionality requirements. To meet performance demands, packet processing systems on routers employ multiple processor cores. We investigate the design of ...
MultiLayer processing - an execution model for parallel stateful packet processing
Mostly emerging network applications comprise deep packet inspection and/or stateful capabilities. Stateful workloads present limitations that reduce the exploitation of parallelism, unlike other network applications that show marginal dependencies ...
BRICK: a novel exact active statistics counter architecture
In this paper, we present an exact active statistics counter architecture called BRICK (Bucketized Rank Indexed Counters) that can efficiently store per-flow variable-width statistics counters entirely in SRAM while supporting both fast updates and ...
Packet prediction for speculative cut-through switching
The amount of intelligent packet processing in an Ethernet switch continues to grow, in order to support of embedded applications such as network security, load balancing and quality of service assurance. This increased packet processing is contributing ...
A programmable architecture for scalable and real-time network traffic measurements
Accurate and real-time traffic measurement is becoming increasingly critical for large variety of applications including accounting, bandwidth provisioning and security analysis. Existing network measurement techniques, however, have major difficulty ...
Adaptive scheduling to maximize NIC throughput in a COTS router
In routers based on commodity off-the-shelf (COTS) hardware and open-source operating systems, there are correlations between the transmission and reception capabilities of individual network interface cards (NICs) and multiple NICs on the same bus ...
Input-queued switches with logarithmic delay: necessary conditions and a reconfigurable scheduling algorithm
Typically, a scheduling algorithm for an n x n packet switch with a crossbar as the data fabric divides time into slots, each of duration tp sufficient to transmit a packet. If a scheduling round requires tr > tp time, then the switch can transmit ...
SimNP: a flexible platform for the simulation of a network processing system
In this paper we present an open source flexible network processor simulation framework called SimNP. Allowing algorithms and applications to be implemented in high level languages such as C or C++, SimNP allows workload characterization, architecture ...
Towards effective network algorithms on multi-core network processors
To build high-performance network devices with holistic security protection, a large number of algorithms have been proposed. However, multi-core implementation of the existing algorithms suffers from three limitations: performance instability, data-...
Performing time-sensitive network experiments
It is commonly believed that the Internet has deficiencies that need to be fixed. However, making changes to the current Internet infrastructure is not easy, if possible at all. Any new protocol or design to be implemented on a global scale requires ...
Data path credentials for high-performance capabilities-based networks
Capabilities-based networks present a fundamental shift in the security design of network architectures. Instead of permitting the transmission of packets from any source to any destination, routers deny forwarding by default. For a successful ...
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Internet traffic. With everincreasing ruleset size and line speed, the task of ...
Stateful hardware decompression in networking environment
Compression and Decompression can significantly lower the network bandwidth requirements for common internet traffic. Driven by the demands of an enterprise network intrusion system, this paper defines and examines the requirements of popular dictionary-...
On design of bandwidth scheduling algorithms for multiple data transfers in dedicated networks
The significance of high-performance dedicated networks has been well recognized due to the rapidly increasing number of large-scale applications that require high-speed data transfer. Efficient algorithms are needed for path computation and bandwidth ...
Software techniques to improve virtualized I/O performance on multi-core systems
Virtualization technology is now widely deployed on high performance networks such as 10-Gigabit Ethernet (10GE). It offers useful features like functional isolation, manageability and live migration. Unfortunately, the overhead of network I/O ...
Design optimization of a highly parallel InfiniBand host channel adapter
Network processors use highly parallel architectures to improve performance and reach multi-gigabit line-speeds. In this paper, we emulate a pipeline in a highly parallel non-programmable industrial InfiniBand Host Channel Adapter to make a performance ...