Input-queued switches with logarithmic delay: necessary conditions and a reconfigurable scheduling algorithm
Abstract
References
Index Terms
- Input-queued switches with logarithmic delay: necessary conditions and a reconfigurable scheduling algorithm
Recommendations
Frame-Based Packet-Mode Scheduling for Input-Queued Switches
Most packet scheduling algorithms for input-queued switches operate on fixed-sized packets known as cells. In reality, communication traffic in many systems such as Internet runs on variable-sized packets. Motivated by potential savings of segmentation ...
An efficient packet scheduling algorithm with deadline guarantees for input-queued switches
Input-queued (IQ) switches overcome the scalability problem suffered by output-queued switches. In order to provide differential quality of services (QoS), we need to efficiently schedule a set of incoming packets so that every packet can be transferred ...
A logarithmic scheduling algorithm for high speed input-queued switches
Throughput of input queued switches using FIFOs is limited due to the Head of Line blocking (HoL) problem. Using VOQs at inputs and a proper scheduling algorithm, near 100% throughput can be achieved. Scaling in terms of number of ports and line rates ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
- General Chair:
- Mark Franklin,
- Program Chairs:
- D. K. Panda,
- Dimitri Stiliadis
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Check for updates
Author Tags
Qualifiers
- Poster
Funding Sources
Conference
Acceptance Rates
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 134Total Downloads
- Downloads (Last 12 months)1
- Downloads (Last 6 weeks)0
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in