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Power consumption in the register file (RF) forms a considerable fraction of the total power consumption in a chip. With increasing instruction window sizes and issue widths, RF power consumption will suffer a significantly large growth. Using the fact ...

This paper investigates some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in performance. The basic idea is to combine different threshold voltages with ...

The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. In this paper, we present a novel technique to reduce register requirements as well as their dynamic and static power dissipation ...

A novel low power multiplication algorithm for reducing switching activity through operand decomposition is proposed. Our experimental results show 12% to 18% reduction in logic transitions in both array multipliers and tree multipliers of 32 bits and 64 ...

This paper presents a method to address state explosion in timed circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a ...

Due to their simplicity transition faults are often used as targets for test generation to detect delay defects. However, one concern documented in the literature is that of over testing. One of the reasons for overtesting is that DFT approaches, such as ...

The essence of existing methods to simulate crosstalk pulse faults in sequential circuits is the use of logic wave form on each line in the circuit. Explicitly keeping track of timing information is costly in terms of memory usage and computational effort. ...

Multiple clock domains are a challenge for hardware specification and verification. We present a method for specifying the relations between multiple clocks, and for modeling the possible behaviors. We can then verify a hardware design assuming that the ...

The computational time and memory of three-dimensional (3-D) capacitance extraction have been greatly reduced by using a quasi-multiple medium (QMM)technology, because it enlarges the matrix sparsity produced by the direct boundary element method (BEM). In ...

In this paper, we present a fast, segment-based approach to estimate the functional coupled-noise value at the receiver pins of a net with minimal loss of accuracy. The net is suitably modeled into segments consisting of two-pi, three-pi or four-pimodels. ...

As process geometries shrink, leakage current is becoming an increasing lycritical problem, especially in full-custom circuit de-signs. Excessive leakage may cause functional failure at some or all operating conditions. Traditional circuit analysis ...

Analyzing the effect of crosstalk on delay is critical for high performance circuits. The major bottleneck in performing crosstalk-induced delay analysis is the high computational cost of simulating the coupled interconnect and the nonlinear drivers. In ...

A compact model for analysis and design of the power distribution network with on-chip decoupling capacitor for high-power blocks is presented. The model is applied to a high-density content addressable memory (CAM) for verification. Utilizing HSIM, a ...

This paper presents a precomputation-based guarding technique to reduce both dynamic and static power consumptions in CMOS VLSI circuits. More precisely, a high threshold sleep transistor is placed in series with some portions of the circuit. Based on the ...

This paper describes an energy-efficient means to achieve on-chip dc-dc conversion for dynamic energy-performance trade-offs in digital circuits. The approach uses balanced voltage islands running at fractions of the supply voltage. Charge "discarded" by ...

Demands for the low power VLSI have been pushing thedevelopment of aggressive design methodologies to reducethe power consumption drastically. To meet the growingdemand, we propose a low power adder, which adaptivelyselects supply voltages based on the ...

We present a new method that facilitates low-to-high voltage conversion in dual-supply-voltage systems. This method leverages from the operation principles of dynamic precharged gates to completely eliminate the area and delay overhead incurred by explicit ...

DNA probe arrays have recently emerged as one of the core genomic technologies. Exploiting analogies between manufacturing processes for DNA arrays and for VLSI chips, we demonstrate the potential for transfer of methodologies from the 40-year old field of ...

System level design always has a disadvantage of not possessing detailed knowledge of the communication sub-system. This is a crucial issue for System-on-Chip design, where uncertainty in communication by very deep submicron effects cannot be neglected. ...

It is becoming necessary to have finer granularity and control of clock domains in System-on-Chip (SoC) designs for various reasons, power consumption being the primary consideration. In this work we have developed a mechanism to support frequency islands ...

Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) as a programmable co-processor to reduce the computational load on the main processor core. In this paper, we present an interface synthesis approach that ...

We propose an efficient heuristic for the constraint-driven communication synthesis (CDCS) of on-chip communication networks. The complexity of the synthesis problems comes from the number of constraints that have to be considered. In this paper we propose ...