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Efficient Synthesis of Networks On Chip

Published: 13 October 2003 Publication History

Abstract

We propose an efficient heuristic for the constraint-driven communication synthesis (CDCS) of on-chip communication networks. The complexity of the synthesis problems comes from the number of constraints that have to be considered. In this paper we propose to cluster constraints to reduce the number that needs to be considered by the optimization algorithm. Then a quadratic programming approach is used to solve the communication synthesis problem with the clustered constraints. We provide an analytical model that justifies our choice of the clustering cost function and we discuss a set of experiments showing the effectiveness of the overall approach with respect to the exact algorithm.

Cited By

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  • (2016)Fine-Grained Interconnect SynthesisACM Transactions on Reconfigurable Technology and Systems10.1145/28926419:4(1-22)Online publication date: 11-Aug-2016
  • (2016)Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-InterconnectACM Transactions on Design Automation of Electronic Systems10.1145/289049921:3(1-23)Online publication date: 21-Jul-2016
  • (2015)Fine-Grained Interconnect SynthesisProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689061(46-55)Online publication date: 22-Feb-2015
  • Show More Cited By

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Published In

cover image Guide Proceedings
ICCD '03: Proceedings of the 21st International Conference on Computer Design
October 2003
ISBN:0769520251

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IEEE Computer Society

United States

Publication History

Published: 13 October 2003

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Cited By

View all
  • (2016)Fine-Grained Interconnect SynthesisACM Transactions on Reconfigurable Technology and Systems10.1145/28926419:4(1-22)Online publication date: 11-Aug-2016
  • (2016)Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-InterconnectACM Transactions on Design Automation of Electronic Systems10.1145/289049921:3(1-23)Online publication date: 21-Jul-2016
  • (2015)Fine-Grained Interconnect SynthesisProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689061(46-55)Online publication date: 22-Feb-2015
  • (2013)Designing best effort networks-on-chip to meet hard latency constraintsACM Transactions on Embedded Computing Systems10.1145/2485984.248599612:4(1-23)Online publication date: 3-Jul-2013
  • (2011)A tree-based topology synthesis for on-chip networkProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132471(651-658)Online publication date: 7-Nov-2011
  • (2010)A method to remove deadlocks in networks-on-chips with wormhole flow controlProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871318(1625-1628)Online publication date: 8-Mar-2010
  • (2010)ACESProceedings of the 47th Design Automation Conference10.1145/1837274.1837385(443-448)Online publication date: 13-Jun-2010
  • (2010)Networks on ChipsProceedings of the 47th Design Automation Conference10.1145/1837274.1837352(300-305)Online publication date: 13-Jun-2010
  • (2010)CAPPSIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200930418:2(209-221)Online publication date: 1-Feb-2010
  • (2010)Comparative analysis of NoCs for two-dimensional versus three-dimensional SoCs supporting multiple voltage and frequency islandsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2010.204732057:5(364-368)Online publication date: 1-May-2010
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