Transmission Gate based Keeper Control for Domino Logic Circuits

Design of domino logic circuits at lower technology nodes, require a keeper circuit to facilitate replenishing of dynamic node against charge leakage and charge sharing. However, this imparts reduction in operating speed and robustness. To overcome this, the proposed work focus on the design of a novel Transmission Gate based Clock Delayed Dual Keeper Domino Logic topology (TG_CDDK) and PMOS Transmission Gate based Clock Delayed Dual Keeper Domino Logic topology (PMOS_TG_CDDK) . The proposed keeper circuit comprises two keeper transistors in series and is controlled by a transmission gate configuration. Using this TG_CDDK, the keeper circuit is enabled only after a delay during the initial evaluation phase. This facilitate faster discharge of the dynamic node without any contention on the pull-down network (PDN) evaluating a TRUE condition. Further, the decrease in the feedback loop gain eliminates the aggravation of the variability effects while the circuit is continuously operated. The circuit was designed and simulated using Cadence® Virtuoso with 180nm technology library. The ADEL spectre results demonstrate 39.8% and 37.7% increase in speed in the proposed designs over the conventional domino logic and an optimal delay variability of 8.02% and 7.11% while subjected to 2000 runs using ADEXL.