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Towards low-power embedded vector processor

Authors:

Adrian CristalAuthors Info & Claims

CF '16: Proceedings of the ACM International Conference on Computing Frontiers

Pages 339 - 342

https://doi.org/10.1145/2903150.2903485

Published: 16 May 2016 Publication History

Abstract

In the low-end mobile processor market, power, energy and area budgets are significantly lower than in the server/desktop/laptop/high-end mobile markets. It has been shown that vector processors are a highly energy-efficient way to increase performance but adding support for them incurs area and power overheads that could not be acceptable for low-end mobile processors. In this work, we propose an integrated vector-scalar design that mostly reuses scalar hardware to support the execution of vector instructions. The key element of the design is our proposed block-based model of execution that groups vector computational instructions to execute them coordinately.

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Cited By

Ma WHuang LDeng LCheng YYang LTong GYan RLan MZhang JXu W(2022)High-efficiency vector and scalar fused load store unit designInternational Conference on High Performance Computing and Communication (HPCCE 2021)10.1117/12.2628136(36)Online publication date: 18-Feb-2022
https://doi.org/10.1117/12.2628136
Rajeshwari BVeena K(2017)MIMO receiver and decoder using vector processorTENCON 2017 - 2017 IEEE Region 10 Conference10.1109/TENCON.2017.8228044(1225-1230)Online publication date: Nov-2017
https://doi.org/10.1109/TENCON.2017.8228044

Index Terms

Towards low-power embedded vector processor
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Single instruction, multiple data

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Information

Published In

cover image ACM Conferences

CF '16: Proceedings of the ACM International Conference on Computing Frontiers

May 2016

487 pages

ISBN:9781450341288

DOI:10.1145/2903150

General Chairs:
Gianluca Palermo
Politecnico di Milano, IT
,
John Feo
Pacific Northwest National Laboratory and Northwest Institute for Advanced Computing
,
Program Chairs:
Antonino Tumeo
Pacific Northwest National Laboratory, USA
,
Hubertus Franke
New York University and IBM Research, USA

Copyright © 2016 Owner/Author.

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

Sponsors

Micron Foundation: Micron Technology Foundation, Inc.
ACM: Association for Computing Machinery
Politecnico di Milano: Politecnico di Milano
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IBM: IBM

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 May 2016

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CF'16

Sponsor:

Micron Foundation
ACM
Politecnico di Milano
SIGMICRO
IBM

CF'16: Computing Frontiers Conference

May 16 - 19, 2016

Como, Italy

Acceptance Rates

CF '16 Paper Acceptance Rate 30 of 94 submissions, 32%;

Overall Acceptance Rate 273 of 785 submissions, 35%

Upcoming Conference

CF '25

Sponsor:
sigmicro

22nd ACM International Conference on Computing Frontiers

May 28 - 30, 2025

Cagliari , Italy

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Cited By

Ma WHuang LDeng LCheng YYang LTong GYan RLan MZhang JXu W(2022)High-efficiency vector and scalar fused load store unit designInternational Conference on High Performance Computing and Communication (HPCCE 2021)10.1117/12.2628136(36)Online publication date: 18-Feb-2022
https://doi.org/10.1117/12.2628136
Rajeshwari BVeena K(2017)MIMO receiver and decoder using vector processorTENCON 2017 - 2017 IEEE Region 10 Conference10.1109/TENCON.2017.8228044(1225-1230)Online publication date: Nov-2017
https://doi.org/10.1109/TENCON.2017.8228044

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