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Article

The Vector-Thread Architecture

Authors:

Ronny Krashinsky,

Christopher Batten,

Krste AsanovicAuthors Info & Claims

ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture

Page 52

Published: 02 March 2004 Publication History

Abstract

The vector-thread (VT) architectural paradigm unifies the vectorand multithreaded compute models. The VT abstraction providesthe programmer with a control processor and a vector of virtualprocessors (VPs). The control processor can use vector-fetch commandsto broadcast instructions to all the VPs or each VP can usethread-fetches to direct its own control flow. A seamless intermixingof the vector and threaded control mechanisms allows a VT architectureto flexibly and compactly encode application parallelismand locality, and a VT machine exploits these to improve performanceand efficiency. We present SCALE, an instantiation of theVT architecture designed for low-power and high-performance embeddedsystems. We evaluate the SCALE prototype design usingdetailed simulation of a broad range of embedded applications andshow that its performance is competitive with larger and more complexprocessors.

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Information & Contributors

Information

Published In

cover image ACM Conferences

ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture

June 2004

373 pages

ISBN:0769521436

ACM SIGARCH Computer Architecture News Volume 32, Issue 2
ISCA 2004
March 2004
373 pages
ISSN:0163-5964
DOI:10.1145/1028176
Issue’s Table of Contents

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

IEEE Computer Society

United States

Publication History

Published: 02 March 2004

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Article

Conference

ISCA04

Sponsor:

SIGARCH

ISCA04: The 31st Annual International Symposium on Computer Architecture 2004

June 19 - 23, 2004

München, Germany

Acceptance Rates

ISCA '04 Paper Acceptance Rate 31 of 217 submissions, 14%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

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Cited By

Zhang ZOu YLiu YWang CZhou YWang XZhang YOuyang YShan JWang YXue JCui HFeng XAamodt TJerger NSwift M(2023)Occamy: Elastically Sharing a SIMD Co-processor across Multiple CPU CoresProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582046(483-497)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3582016.3582046
Gobieski GAtli AMai KLucia BBeckmann NMartínez JDuato JJohn L(2021)SnafuProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00084(1027-1040)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00084
Dadu VWeng JLiu SNowatzki T(2019)Towards General Purpose Acceleration by Exploiting Common Data-Dependence FormsProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358276(924-939)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358276
Nowatzki TGangadhar VArdalani NSankaralingam K(2017)Stream-Dataflow AccelerationACM SIGARCH Computer Architecture News10.1145/3140659.308025545:2(416-429)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080255
Kim JJiang STorng CWang MSrinath SIlbeyi BAl-Hawaj KBatten CHunter HMoreno JEmer JSanchez D(2017)Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programsProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3136952(759-773)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3136952
Nowatzki TGangadhar VArdalani NSankaralingam K(2017)Stream-Dataflow AccelerationProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080255(416-429)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3079856.3080255
Stanic MPalomar OHayes TRatkovic ICristal AUnsal OValero M(2017)An Integrated Vector-Scalar Design on an In-Order ARM CoreACM Transactions on Architecture and Code Optimization10.1145/307561814:2(1-26)Online publication date: 26-May-2017
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Baghsorkhi SVasudevan NWu Y(2016)FlexVec: auto-vectorization for irregular loopsACM SIGPLAN Notices10.1145/2980983.290811151:6(697-710)Online publication date: 2-Jun-2016
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Baghsorkhi SVasudevan NWu YKrintz CBerger E(2016)FlexVec: auto-vectorization for irregular loopsProceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/2908080.2908111(697-710)Online publication date: 2-Jun-2016
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Stanic MPalomar OHayes TRatkovic IUnsal OCristal APalermo GFeo JTumeo AFranke H(2016)Towards low-power embedded vector processorProceedings of the ACM International Conference on Computing Frontiers10.1145/2903150.2903485(339-342)Online publication date: 16-May-2016
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