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On the trade-off between power and flexibility of FPGA clock networks

Authors:

Julien Lamoureux,

Steven J. E. WiltonAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 1, Issue 3

Article No.: 13, Pages 1 - 33

https://doi.org/10.1145/1391732.1391733

Published: 19 September 2008 Publication History

Abstract

FPGA clock networks consume a significant amount of power, since they toggle every clock cycle and must be flexible enough to implement the clocks for a wide range of different applications. The efficiency of FPGA clock networks can be improved by reducing this flexibility; however, reducing the flexibility introduces stricter constraints during the clustering and placement stages of the FPGA CAD flow. These constraints can reduce the overall efficiency of the final implementation. This article examines the trade-off between the power consumption and flexibility of FPGA clock networks.

Specifically, this article makes three contributions. First, it presents a new parameterized clock-network framework for describing and comparing FPGA clock networks. Second, it describes new clock-aware placement techniques that are needed to find a legal placement satisfying the constraints imposed by the clock network. Finally, it performs an empirical study to examine the trade-off between the power consumption of the clock network and the impact of the CAD constraints for a number of different clock networks with varying amounts of flexibility.

The results show that the techniques used to produce a legal placement can have a significant influence on power and the ability of the placer to find a legal solution. On average, circuits placed using the most effective techniques dissipate 5% less overall energy and are significantly more likely to be legal than circuits placed using other techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network are up to 14.6% more energy efficient compared to other FPGAs.

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Cited By

Li WDehkordi MYang SPan DBazargan KNeuendorffer S(2019)Simultaneous Placement and Clock Tree Construction for Modern FPGAsProceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3289602.3293897(132-141)Online publication date: 20-Feb-2019
https://dl.acm.org/doi/10.1145/3289602.3293897
Li WLin YLi MDhar SPan D(2018)UTPlaceF 2.0ACM Transactions on Design Automation of Electronic Systems10.1145/317484923:4(1-23)Online publication date: 9-May-2018
https://dl.acm.org/doi/10.1145/3174849
Ebeling CHow DLewis DSchmit HChen DGreene J(2016)Stratix™ 10 High Performance Routable Clock NetworksProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847279(64-73)Online publication date: 21-Feb-2016
https://dl.acm.org/doi/10.1145/2847263.2847279
Show More Cited By

Index Terms

On the trade-off between power and flexibility of FPGA clock networks
1. Hardware

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 1, Issue 3

September 2008

135 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/1391732

Issue’s Table of Contents

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 September 2008

Accepted: 01 April 2008

Revised: 01 March 2008

Received: 01 July 2007

Published in TRETS Volume 1, Issue 3

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Cited By

Li WDehkordi MYang SPan DBazargan KNeuendorffer S(2019)Simultaneous Placement and Clock Tree Construction for Modern FPGAsProceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3289602.3293897(132-141)Online publication date: 20-Feb-2019
https://dl.acm.org/doi/10.1145/3289602.3293897
Li WLin YLi MDhar SPan D(2018)UTPlaceF 2.0ACM Transactions on Design Automation of Electronic Systems10.1145/317484923:4(1-23)Online publication date: 9-May-2018
https://dl.acm.org/doi/10.1145/3174849
Ebeling CHow DLewis DSchmit HChen DGreene J(2016)Stratix™ 10 High Performance Routable Clock NetworksProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847279(64-73)Online publication date: 21-Feb-2016
https://dl.acm.org/doi/10.1145/2847263.2847279
Jevtic RCarreras C(2012)A complete dynamic power estimation model for data-paths in FPGA DSP designsIntegration, the VLSI Journal10.1016/j.vlsi.2011.09.00245:2(172-185)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1016/j.vlsi.2011.09.002
Easwaran LAkoglu A(2011)Net-length-based routability-driven power-aware clusteringACM Transactions on Reconfigurable Technology and Systems10.1145/2068716.20687244:4(1-16)Online publication date: 28-Dec-2011
https://dl.acm.org/doi/10.1145/2068716.2068724
Becker TJamieson PLuk WCheung PRissa T(2010)Power characterisation for fine-grain reconfigurable fabricsInternational Journal of Reconfigurable Computing10.1155/2010/7874052010(2-2)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1155/2010/787405
Becker TLuk WCheung P(2010)Energy-Aware Optimisation for Run-Time ReconfigurationProceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2010.17(55-62)Online publication date: 2-May-2010
https://dl.acm.org/doi/10.1109/FCCM.2010.17
Yang MHongying Xu Almaini A(2009)Power-aware FPGA packing algorithm2009 IEEE 8th International Conference on ASIC10.1109/ASICON.2009.5351571(817-819)Online publication date: Oct-2009
https://doi.org/10.1109/ASICON.2009.5351571

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