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A simulation based study of TLB performance

Authors:

J. Bradley Chen,

Anita Borg,

Norman P. JouppiAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 20, Issue 2

Pages 114 - 123

https://doi.org/10.1145/146628.139708

Published: 01 April 1992 Publication History

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Abstract

This paper presents the results of a simulation-based study of various translation lookaside buffer (TLB) architectures, in the context of a modern VLSI RISC processor. The simulators used address traces, generated by instrumented versions of the SPEC marks and several other programs running on a DECstation 5000. The performance of two-level TLBs and fully-associative TLBs were investigated. The amount of memory mapped was found to be the dominant factor in TLB performance. Small first-level FIFO instruction TLBs can be effective in two level TLB configurations. For some applications, the cyles-per-instruction (CPI) loss due to TLB misses can be reduced from as much as 5CPI to negligible levels with typical TLB parameters through the use of variable-sized pages.

References

[1]

J. F. Bartlett. SCHEME->C: A Portable Scheme-to-C Compiler. WRL Research Report 89/1, Digital Equipment Western Research Laboratory, 1989.

Google Scholar

[2]

Anita Borg, R.E. Kessler, Georgia Lazana, and David Wall. Long Address Traces from RISC Machines: Generation and Analysis. WRL Research Report 89/14, Digital Equipment Western Research Laboratory, 1989.

Google Scholar

[3]

Douglas W. Clark and Joel S. Emer. "Performance of the VAX 11/780 Translation Buffer: Simulation and Measurement.". ACM Transactions on Computer Systems 3, 1 (February 1985).

Digital Library

Google Scholar

[4]

Douglas W. Clark, Peter J. Bannon, and James B. Keller. Measuring VAX 8800 Performance with a Histogram Hardware Monitor. Proceedings of the 15th Annual International Symposium on Computer Architecture, June, 1988, pp. 176-185.

Digital Library

Google Scholar

[5]

Daniel Dobberpuhl, et. al. A 200Mhz 64b Dual-issue CMOS Microprocessor. The 39th International Solid-State Circuits Conference, IEEE Computer Society Press, February, 1992, pp. 106-107. See also slide supplement.

Google Scholar

[6]

Norman P. Jouppi. Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU. Proceedings of the 16th Annual International Symposium on Computer Architecture, May, 1989, pp. 281-289.

Digital Library

Google Scholar

[7]

Sunil Mirapuri, Michael Woodacre, and Nader Vasseghi. "The MIPS R4000 Processor". IEEE Micro 12, 4 (April 1992),.

Digital Library

Google Scholar

[8]

J. Ousterhout, G. Hamachi, R. Mayo, W. Scott, and G.S. Taylor. "The Magic VLSI Layout System". IEEE Design and Test of Computers 2, 1 (February 1985), 19-30.

Digital Library

Google Scholar

[9]

Steven A. Przybylski. Cache Design: A Performance- Directed Approach. Morgan-Kaufmann, San Mateo, CA, 1990.

Digital Library

Google Scholar

[10]

Alan Jay Smith. "Cache Memories". ACM Computer Surveys 14, 3 (September 1982), 473-530.

Digital Library

Google Scholar

[11]

David A. Wood, et. al. An In-Cache Address Translation Mechanism. The 13th Annual Symposium on Computer Architecture, IEEE Computer Society Press, June, 1986, pp. 358-365.

Digital Library

Google Scholar

[12]

David A. Wood. The Design and Evaluation of ln- Cache Address Translation. Ph.D. Th., Department of Computer Science, UC Berkeley, March 1991. Report Number UCB/CSD 90/565.

Digital Library

Google Scholar

Cited By

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Park YBahn H(2020)Issues in File Caching and Virtual Memory Paging with Fast SCM StorageAdvances in Science, Technology and Engineering Systems Journal10.25046/aj0505815:5(660-668)Online publication date: 2020
https://doi.org/10.25046/aj050581
Mittal S(2016)A survey of techniques for architecting TLBsConcurrency and Computation: Practice and Experience10.1002/cpe.406129:10Online publication date: 22-Dec-2016
https://doi.org/10.1002/cpe.4061
Tong XKoju TKawahito MMoshovos A(2015)Optimizing Memory Translation Emulation in Full System EmulatorsACM Transactions on Architecture and Code Optimization10.1145/268603411:4(1-24)Online publication date: 9-Jan-2015
https://dl.acm.org/doi/10.1145/2686034
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A simulation based study of TLB performance

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 20, Issue 2

Special Issue: Proceedings of the 19th annual international symposium on Computer architecture (ISCA '92)

May 1992

429 pages

ISSN:0163-5964

DOI:10.1145/146628

Editor:
Allan Gotlieb
New York Univ., New York, NY

Issue’s Table of Contents

ISCA '92: Proceedings of the 19th annual international symposium on Computer architecture
May 1992
439 pages
ISBN:0897915097
DOI:10.1145/139669
Chairman:
Allan Gottlieb
New York Unvi., New York, NY

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1992

Published in SIGARCH Volume 20, Issue 2

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Park YBahn H(2020)Issues in File Caching and Virtual Memory Paging with Fast SCM StorageAdvances in Science, Technology and Engineering Systems Journal10.25046/aj0505815:5(660-668)Online publication date: 2020
https://doi.org/10.25046/aj050581
Mittal S(2016)A survey of techniques for architecting TLBsConcurrency and Computation: Practice and Experience10.1002/cpe.406129:10Online publication date: 22-Dec-2016
https://doi.org/10.1002/cpe.4061
Tong XKoju TKawahito MMoshovos A(2015)Optimizing Memory Translation Emulation in Full System EmulatorsACM Transactions on Architecture and Code Optimization10.1145/268603411:4(1-24)Online publication date: 9-Jan-2015
https://dl.acm.org/doi/10.1145/2686034
Srikantaiah SKandemir M(2010)Synergistic TLBs for High Performance Address Translation in Chip MultiprocessorsProceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2010.26(313-324)Online publication date: 4-Dec-2010
https://dl.acm.org/doi/10.1109/MICRO.2010.26
Bhattacharjee AMartonosi M(2009)Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip MultiprocessorsProceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2009.26(29-40)Online publication date: 12-Sep-2009
https://dl.acm.org/doi/10.1109/PACT.2009.26
Park CPark D(2001)Aggressive superpage support with the shadow memory and the partial-subblock TLBMicroprocessors and Microsystems10.1016/S0141-9331(01)00125-925:7(329-342)Online publication date: Oct-2001
https://doi.org/10.1016/S0141-9331(01)00125-9
Stojkovic JMantri NSkarlatos DXu TTorrellas J(2023)Memory-Efficient Hashed Page Tables2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071061(1221-1235)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071061
Hernández C. ALin WHong JBures MPark JCerny T(2022)Effective TLB thrashingProceedings of the 37th ACM/SIGAPP Symposium on Applied Computing10.1145/3477314.3507110(1704-1712)Online publication date: 25-Apr-2022
https://dl.acm.org/doi/10.1145/3477314.3507110
Yang YYe HChen YLiu XTalati NHe XMudge TDreslinski R(2020)CoPTA: Contiguous Pattern Speculating TLB ArchitectureEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-60939-9_5(67-83)Online publication date: 7-Oct-2020
https://doi.org/10.1007/978-3-030-60939-9_5
Elnawawy HChowdhury RAwad AByrd GEigenmann RDing CMcKee S(2019)Diligent TLBsProceedings of the ACM International Conference on Supercomputing10.1145/3330345.3330363(195-205)Online publication date: 26-Jun-2019
https://dl.acm.org/doi/10.1145/3330345.3330363
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