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An in-cache address translation mechanism

Authors:

J. M. PendletonAuthors Info & Claims

ISCA '86: Proceedings of the 13th annual international symposium on Computer architecture

Pages 358 - 365

Published: 01 May 1986 Publication History

Abstract

In the design of SPUR, a high-performance multiprocessor workstation, the use of large caches and hardware-supported cache consistency suggests a new approach to virtual address translation. By performing translation in each processor's virtually-tagged cache, the need for separate translation lookaside buffers (TLBs) is eliminated. Eliminating the TLB substantially reduces the hardware cost and complexity of the translation mechanism and eliminates the translation consistency problem. Trace-driven simulations show that normal cache behavior is only minimally affected by caching page table entries, and that in many cases, using a separate device would actually reduce system performance.

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Cited By

Chen DTong DYang CYi JCheng X(2023)FlexPointer: Fast Address Translation Based on Range TLB and Tagged PointersACM Transactions on Architecture and Code Optimization10.1145/357985420:2(1-24)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1145/3579854
Gupta SBhattacharyya AOh YBhattacharjee AFalsafi BPayer MMartínez JDuato JJohn L(2021)Rebooting virtual memory with midgardProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00047(512-525)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00047
Yoon HLowe-Power JSohi G(2018)Filtering Translation Bandwidth with Virtual CachingACM SIGPLAN Notices10.1145/3296957.317319553:2(113-127)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3173195
Show More Cited By

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An in-cache address translation mechanism

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An in-cache address translation mechanism
Special Issue: Proceedings of the 13th annual international symposium on Computer architecture (ISCA '86)

In the design of SPUR, a high-performance multiprocessor workstation, the use of large caches and hardware-supported cache consistency suggests a new approach to virtual address translation. By performing translation in each processor's virtually-tagged ...
Design and Evaluation of In-Cache Address Translation
Use of superpages and subblocking in the address translation hierarchy

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Information & Contributors

Information

Published In

cover image ACM Conferences

ISCA '86: Proceedings of the 13th annual international symposium on Computer architecture

June 1986

454 pages

ISBN:081860719X

Chairman:
Hideo Aiso

ACM SIGARCH Computer Architecture News Volume 14, Issue 2
Special Issue: Proceedings of the 13th annual international symposium on Computer architecture (ISCA '86)
May 1986
429 pages
ISSN:0163-5964
DOI:10.1145/17356
Editor:
Hideo Aiso
Issue’s Table of Contents

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SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 May 1986

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Cited By

Chen DTong DYang CYi JCheng X(2023)FlexPointer: Fast Address Translation Based on Range TLB and Tagged PointersACM Transactions on Architecture and Code Optimization10.1145/357985420:2(1-24)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1145/3579854
Gupta SBhattacharyya AOh YBhattacharjee AFalsafi BPayer MMartínez JDuato JJohn L(2021)Rebooting virtual memory with midgardProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00047(512-525)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00047
Yoon HLowe-Power JSohi G(2018)Filtering Translation Bandwidth with Virtual CachingACM SIGPLAN Notices10.1145/3296957.317319553:2(113-127)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3173195
Yoon HLowe-Power JSohi GShen XTuck JBianchini RSarkar V(2018)Filtering Translation Bandwidth with Virtual CachingProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173195(113-127)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3173162.3173195
Parasar MBhattacharjee AKrishna T(2018)SEESAWProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00026(193-206)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00026
Gandhi JHill MSwift M(2016)Agile pagingACM SIGARCH Computer Architecture News10.1145/3007787.300121244:3(707-718)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1145/3007787.3001212
Park CHeo THuh J(2016)Efficient synonym filtering and scalable delayed translation for hybrid virtual cachingACM SIGARCH Computer Architecture News10.1145/3007787.300116044:3(217-229)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1145/3007787.3001160
Park CHeo THuh J(2016)Efficient synonym filtering and scalable delayed translation for hybrid virtual cachingACM SIGARCH Computer Architecture News10.1145/3007787.300114744:3(90-102)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1145/3007787.3001147
Gandhi JHill MSwift MMin SLoh G(2016)Agile pagingProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.67(707-718)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1109/ISCA.2016.67
Park CHeo THuh JMin SLoh G(2016)Efficient synonym filtering and scalable delayed translation for hybrid virtual cachingProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.28(217-229)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1109/ISCA.2016.28
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