article

A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs

Authors:

Yo-Hao Tu,

Jen-Chieh Liu,

Kuo-Hsing Cheng,

Chih-Hsun HsuAuthors Info & Claims

Analog Integrated Circuits and Signal Processing, Volume 93, Issue 1

Pages 157 - 167

https://doi.org/10.1007/s10470-017-1005-4

Published: 01 October 2017 Publication History

Abstract

This paper proposes a low supply voltage all-digital clock-deskew buffer with in-phase and quadrature phase (I/Q) outputs on an intra-chip. In some application-specific integrated chips or silicon intellectual properties might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, I/Q clock signals are widely adopted in the communication systems and double data rate memories. The proposed all-digital clock-deskew buffer can operate from 220 to 570 MHz at 0.5 V and the power consumption is 1.95 mW at 570 MHz. This buffer can also supply a quadrature phase output using a proposed two-step edge detector.

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Grossi MOmaña M(2019)Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew BuffersJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05788-x35:2(261-267)Online publication date: 25-May-2019
https://dl.acm.org/doi/10.1007/s10836-019-05788-x

A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs
1. Hardware

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cover image Analog Integrated Circuits and Signal Processing

Analog Integrated Circuits and Signal Processing Volume 93, Issue 1

October 2017

177 pages

ISSN:0925-1030

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Kluwer Academic Publishers

United States

Publication History

Published: 01 October 2017

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Grossi MOmaña M(2019)Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew BuffersJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05788-x35:2(261-267)Online publication date: 25-May-2019
https://dl.acm.org/doi/10.1007/s10836-019-05788-x

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0.5 V Supply Resistorless Voltage Reference for Low Voltage Applications

A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V

A charge transfer-based high performance, ultra-low power CMOS charge pump for PLLs

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