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Congestion aware low power on chip protocols with network on chip with cloud security

Published: 09 September 2022 Publication History

Abstract

This article is to analyze the bottleneck problems of NoC in many more applications like multi-processor communication, computer architectures, and network interface processors. This paper aims to research the advantages and disadvantages of low congestion protocols on highway environments like multiple master multiple slave interconnections. A long-term evolution and effective on-chip connectivity solution for secured, congestion aware and low power architecture is emerged for Network-on-Chip (NoC) for MCSoC. Applications running simultaneously on a different chip are often exchanged dynamically on the chip network. Of-course, in general on chip communication, resources mean that applications may interact with shared resources to influence each other's time characteristics.

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Published In

cover image Journal of Cloud Computing: Advances, Systems and Applications
Journal of Cloud Computing: Advances, Systems and Applications  Volume 11, Issue 1
Dec 2022
1609 pages
ISSN:2192-113X
EISSN:2192-113X
Issue’s Table of Contents

Publisher

Hindawi Limited

London, United Kingdom

Publication History

Published: 09 September 2022
Accepted: 03 August 2022
Received: 23 June 2022

Author Tags

  1. Network-on-Chip
  2. System on Chip
  3. Chip multiprocessor
  4. Congestion
  5. Long term evolution
  6. Embedded transition inversion
  7. Very Large Scale Integration

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