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Article

Translating affine nested-loop programs to process networks

Authors:

Alexandru Turjan,

Ed DeprettereAuthors Info & Claims

CASES '04: Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems

Pages 220 - 229

https://doi.org/10.1145/1023833.1023864

Published: 22 September 2004 Publication History

Abstract

New heterogeneous multiprocessor platforms are emerging that are typically composed of loosely coupled components that exchange data using programmable interconnections. The components can be CPUs or DSPs, specialized IP cores, reconfigurable units, or memories. To program such platform, we use the Process Network (PN) model of computation. The localized control and distributed memory are the two key ingredients of a PN allowing us to program the platforms. The localized control matches the loosely coupled components and the distributed memory matches the style of interaction between the components. To obtain applications in a PN format, we have built the Compaan compiler that translates affine nested-loop programs into functionally equivalent PNs. In this paper, we describe a novel analytical translation procedure we use in our compiler that is based on integer linear programming. The translation procedure consists of four main steps and we will present each step by describing the main idea involved, followed by a representative example.

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Karfa CSarkar DMandal C(2019)Verification of parallelising transformations of KPN modelsIET Cyber-Physical Systems: Theory & Applications10.1049/iet-cps.2018.5008Online publication date: 11-Mar-2019
https://doi.org/10.1049/iet-cps.2018.5008
Bijlsma TBekooij MSmit G(2019)Circular Buffers with Multiple Overlapping Windows for Cyclic Task GraphsTransactions on High-Performance Embedded Architectures and Compilers V10.1007/978-3-662-58834-5_3(39-58)Online publication date: 23-Feb-2019
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Index Terms

Translating affine nested-loop programs to process networks

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cover image ACM Conferences

CASES '04: Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems

September 2004

324 pages

ISBN:1581138903

DOI:10.1145/1023833

General Chairs:
Mary Jane Irwin
Pennsylvania State University
,
Wei Zhao
Texas Instruments
,
Program Chairs:
Luciano Lavagno
Politecnico di Torino/Cadence Labs
,
Scott Mahlke
University of Michigan, Ann Arbor, MI

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 22 September 2004

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CASES04: 2004 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

September 22 - 25, 2004

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Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

Leben JTzanetakis G(2019)Polyhedral Compilation for Multi-dimensional Stream ProcessingACM Transactions on Architecture and Code Optimization10.1145/333099916:3(1-26)Online publication date: 18-Jul-2019
https://dl.acm.org/doi/10.1145/3330999
Karfa CSarkar DMandal C(2019)Verification of parallelising transformations of KPN modelsIET Cyber-Physical Systems: Theory & Applications10.1049/iet-cps.2018.5008Online publication date: 11-Mar-2019
https://doi.org/10.1049/iet-cps.2018.5008
Bijlsma TBekooij MSmit G(2019)Circular Buffers with Multiple Overlapping Windows for Cyclic Task GraphsTransactions on High-Performance Embedded Architectures and Compilers V10.1007/978-3-662-58834-5_3(39-58)Online publication date: 23-Feb-2019
https://doi.org/10.1007/978-3-662-58834-5_3
Bandyopadhyay SBanerjee KKumar ASarkar SGerndt M(2017)PRESGenProceedings of the 2017 Workshop on Software Engineering Methods for Parallel and High Performance Applications10.1145/3085158.3086158(13-20)Online publication date: 26-Jun-2017
https://dl.acm.org/doi/10.1145/3085158.3086158
Stefanov TPimentel ANikolov H(2017)Daedalus: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on ChipsHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_30-1(1-36)Online publication date: 11-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_30-1
Shoshkov TStefanov TKienhuis B(2016)Parametrized system level design: Real-time X-Ray image processing case study2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP.2016.7760793(196-201)Online publication date: Jul-2016
https://doi.org/10.1109/ASAP.2016.7760793
Ambrose JPeddersen JParameswaran SLabios AYachide Y(2014)SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2014.6742901(267-273)Online publication date: Jan-2014
https://doi.org/10.1109/ASPDAC.2014.6742901
Nadezhkin DNikolov HStefanov T(2013)Automated generation of polyhedral process networks from affine nested-loop programs with dynamic loop boundsACM Transactions on Embedded Computing Systems10.1145/2536747.253675013:1s(1-24)Online publication date: 6-Dec-2013
https://dl.acm.org/doi/10.1145/2536747.2536750
Beyranvand Nejad AMolnos AGoossens K(2013)A unified execution model for multiple computation models of streaming applications on a composable MPSoCJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.07.00659:10(1032-1046)Online publication date: 1-Nov-2013
https://dl.acm.org/doi/10.1016/j.sysarc.2013.07.006
Karfa C(2012)Applications of behavioural transformations in embedded system designIETE Technical Review10.4103/0256-4602.10316629:5(372)Online publication date: 2012
https://doi.org/10.4103/0256-4602.103166
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