More Web Proxy on the site http://driver.im/

article

A design flow for partially reconfigurable hardware

Authors:

James IrvineAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 3, Issue 2

Pages 257 - 283

https://doi.org/10.1145/993396.993399

Published: 01 May 2004 Publication History

Abstract

This paper presents a top-down designer-driven design flow for creating hardware that exploits partial run-time reconfiguration. Computer-aided design (CAD) tools are presented, which complement conventional FPGA design environments to enable the specification, simulation (both functional and timing), synthesis, automatic placement and routing, partial configuration generation and control of partially reconfigurable designs. Collectively these tools constitute the dynamic circuit switching CAD framework. A partially reconfigurable Viterbi decoder design is presented to demonstrate the design flow and illustrate possible power consumption reductions and performance improvements through the exploitation of partial reconfiguration.

References

[1]

Brebner, G. 1996. A virtual hardware operating system for the Xilinx XC6200. In Field Programmable Logic and Applications, Darmstadt, Germany, September 1996, R. W. Hartenstein and M. Glesner, eds. Springer-Verlag, Berlin, 327--336.]]

[2]

Brebner, G. 1997. CHASTE: A hardware/software co-design testbed for the Xilinx XC6200. In Reconfigurable Architectures Workshop, Geneva, Switzerland, April 1997, R. W. Hartenstein and V. K. Prasanna, eds. IT Press, Verlag, 16--23.]]

[3]

Callahan, T. J., Hauser, J. R., and Wawrzynek, J. 2000. The GARP architecture and C compiler. IEEE Computer 33, 4, 62--69.]]

Digital Library

[4]

Dandalis, A. and Prasanna, V. K. 2001. Configuration compression for FPGA-based embedded systems. In 9th ACM International Symposium on Field Programmable Gate Arrays, Monterey, California, USA, February 2001, ACM Press, 173--182.]]

[5]

Diana, L. and Kahn, J. M. 1999. Rate-adaptive modulation techniques for infrared wireless communications. In Proceedings of the IEEE International Conference on Communications, Vancouver, B. C., Canada, June 1999, 597--603.]]

[6]

Dyer, M., Plessl, C., and Platzner, M. 2002. Partially reconfigurable cores for Xilinx virtex. In Field Programmable Logic and Applications, Montpellier, France, September 2002, M. Glesner, P. Zipf, and M. Renovell, eds. Springer-Verlag, Berlin, 292--301.]]

[7]

Faura, J., Moreno, J. M., Madrenas, J., and Insenser, J. M. 1997. VHDL modelling of fast dynamic reconfiguration on novel multicontext RAM-based field-programmable devices. In Proceedings of the SIG-VHDL Spring'97 Working Conference, Toledo, Spain, April 1997, 171--177.]]

[8]

Gokhale, M. B., Stone, J. M., Arnold, J., and Kalinowski, M. 2000. Stream-oriented FPGA computing in the streams-C high level language. In Proceedings of the Eighth Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, California, USA, April 2000, K. L. Pocek and J. Arnold, eds. IEEE Computer Society Press, 49--56.]]

[9]

Goldsmith, A. J. and Chua, S. G. 1998. Adaptive coded modulation for fading channels. IEEE Trans. Commun. 46, 5, 595--602.]]

[10]

Guccione, S., Levi, D., and Sundararajan, P. 1999. JBits: Java-based interface for reconfigurable computing. In Military and Aerospace Applications of Programmable Devices and Technologies Conference, Laurel, MD, September 1999.]]

[11]

Hagenauer, J. and Stockhammer, T., 1999. Channel coding and transmission aspects for wireless multimedia. Proc. IEEE 87, 10, 1764--1777.]]

[12]

Horta, E. L., Lockwood, J. W., Taylor, D. E., and Parlour, D. 2002. Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. In Proceedings of the 39th Design Automation Conference, Los Angeles, USA, June 2002, 343--348.]]

[13]

Hutchings, B., Nelson, B., and Wirthlin, M. J., 2000. Designing and debugging custom computing applications. IEEE Design and Test of Computers 17, 1, 20--28.]]

[14]

Keller, E. 2000. JRoute: A run-time routing API for FPGA hardware. In The Seventh Reconfigurable Architectures Workshop, Cacun, Mexico, May 2000, J. Romlin, ed. Springer-Verlag, Berlin, 874--881.]]

[15]

Kwiat, K. and Debany, W. 1996. Reconfigurable logic modelling. Integrated System Design (Dec.).]]

[16]

Li, Y., Callahan, T., Darnell, E., Harr, R., Kurkure, U., and Stockwood, J., 2000. Hardware--software codesign of embedded reconfigurable architectures. In Proceedings of the 37th Design Automation Conference, Los Angeles, USA, June 2000, 507--512.]]

[17]

Luk, W. and McKeever, S. 1998. Pebble: A language for parameterised and reconfigurable hardware design. In Field Programmable Logic and Applications, Tallinn, Estonia, September 1998, R. W. Hartenstein and A. Keevallik, eds. Springer-Verlag, Berlin, 9--18.]]

[18]

Lysaght, P. and Stockwood, J. 1996. A simulation tool for dynamically reconfigurable field programmable gate arrays. IEEE Trans. VLSI Syst. 4, 3, 381--390.]]

Digital Library

[19]

MacBeth, J., 2003. Dynamically Reconfigurable Intellectual Property Cores (DRIP Cores). Ph.D. Thesis, University of Strathclyde, UK.]]

[20]

McKay, N. and Singh, S. 1999. Debugging techniques for dynamically reconfigurable hardware. In IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, USA, April 1999, K. L. Pocek and J. Arnold, eds., IEEE Computer Society Press, 114--122.]]

[21]

McMillan, S. and Guccione, S. 2000. Partial run-time reconfiguration using JRTR. In Field Programmable Logic and Applications, Villach, Austria, August 2000, R. W. Hartenstein and H. Grunbacher, eds. Springer-Verlag, Berlin, 352--360.]]

[22]

McMillan, S., Blodget, B., and Guccione, S. 2000. VirtexDS: A device simulator for Virtex. Reconfigurable Technology: FPGAs for Computing and Applications II. Proc. SPIE 4212, Bellingham, WA, November 2000.]]

[23]

Randita, B. and Roy, S. K., 1999. Design and implementation of a Viterbi decoder using FPGAs. In 12th International Conference on VLSI Design, Goa, India, January 1999, 611--614.]]

[24]

Robertson, I., Irvine, J., Lysaght, P., and Robinson, D. 2002a. Timing verification of dynamically reconfigurable logic for the Xilinx Virtex FPGA series. In Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA, February 2002, M. Schlag and S. Trimberger, eds. ACM Press, 127--135.]]

[25]

Robertson, I., Irvine, J., Lysaght, P., and Robinson, D. 2002b. Improved functional simulation of dynamically reconfigurable logic. In Field Programmable Logic and Applications, Montpellier, France, September 2002, M. Glesner, P. Zipf, and M. Renovell, eds. Springer-Verlag, Berlin, 152--161.]]

[26]

Robinson, D. 2002. Simulation and Control of Dynamically Reconfigurable Logic Circuits. Ph.D. Thesis, University of Strathclyde, UK.]]

[27]

Robinson, D. and Lysaght, P. 2000a. Methods of exploiting simulation technology for simulating the timing of dynamically reconfigurable logic. IEE Proc. Comput. Digital Tech. 147, 3, 175--180.]]

[28]

Robinson, D. and Lysaght, P. 2000b. Verification of dynamically reconfigurable logic. In Field Programmable Logic and Applications, Villach, Austria, August 2000, R. W. Hartenstein and H. Grunbacher, eds. Springer-Verlag, Berlin, 141--150.]]

[29]

Shirazi, N., Luk, W., and Cheung, P. Y. K. 1998. Automating production of run-time reconfigurable designs. In Proceedings of the Sixth Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, USA, April 1998, K. L. Pocek and J. Arnold, eds. IEEE Computer Society Press, 147--156.]]

[30]

Singh, S. and James-Roxby, P. 2001. Lava and JBits: From HDL to bitstream in seconds. In Proceedings of the Ninth Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Rohnert Park, California, USA, April 2001, K. L. Pocek and J. Arnold, eds. IEEE Computer Society Press.]]

[31]

Swaminathan, S., Tessier, R., Goeckel, D., and Burleson, W. 2002. A dynamically reconfigurable adaptive Viterbi decoder. In Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA, February 2002, M. Schlag and S. Trimberger, eds. ACM Press, 227--236.]]

[32]

Trimberger, S. 1998. Scheduling designs into a time-multiplexed FPGA. In Sixth ACM International Symposium of Field Programmable Gate Arrays, Monterey, California, USA, February 1998, ACM Press, 153--160.]]

Digital Library

[33]

Tripp, J. L., Jackson, P. A., and Hutchings, B. L. 2002. Sea cucumber: A synthesizing compiler for FPGAs. In Field Programmable Logic and Applications, Montpellier, France, September 2002, M. Glesner, P. Zipf, and M. Renovell, eds. Springer-Verlag, Berlin, 875--885.]]

[34]

Vasilko, M. 1999. DYNASTY: A temporal floorplanning based CAD framework for dynamically reconfigurable logic systems. In Field Programmable Logic and Applications, Glasgow, UK, August 1999, P. Lysaght, J. Irvine and R. W. Hartenstein, eds. Springer-Verlag, Berlin, 124--133.]]

[35]

Vasilko, M. and Cabanis, D. 1999. A technique for modelling dynamic reconfiguration with improved simulation accuracy. IEICE Trans. Fundam. Electron., Commun. Comput. Sci. E82-A, 11, 2465--2474.]]

[36]

Xilinx, Inc. 2002. XAPP290: An Implementation Flow for Active Partial Reconfiguration Using 4.2i, Application Note, version 0.7, March 2002.]]

[37]

Yang, J., Khandani, A. K., and Tin, N. 2002. Adaptive Modulation and Coding in 3G Wireless Systems. Technical Report UW-E&CE&num;&num;2002-15, University of Waterloo, Waterloo, Ontario, Canada.]]

[38]

Yeh, D., Feygin, G., and Chow, P. 1996. RACER: A reconfigurable constraint-length 14 Viterbi decoder. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, USA, April 1996, K. L. Pocek and J. Arnold, eds. IEEE Computer Society Press, 60--69.]]

Cited By

Gong LDiessel O(2014)Simulation-based functional verification of dynamically reconfigurable systemsACM Transactions on Embedded Computing Systems10.1145/256004213:4(1-23)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2560042
Gong LDiessel OGong LDiessel O(2014)ConclusionsFunctional Verification of Dynamically Reconfigurable FPGA-based Systems10.1007/978-3-319-06838-1_7(151-155)Online publication date: 22-Jul-2014
https://doi.org/10.1007/978-3-319-06838-1_7
Gong LDiessel OGong LDiessel O(2014)Case StudiesFunctional Verification of Dynamically Reconfigurable FPGA-based Systems10.1007/978-3-319-06838-1_5(87-125)Online publication date: 22-Jul-2014
https://doi.org/10.1007/978-3-319-06838-1_5
Show More Cited By

Recommendations

Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures

Reconfigurable hybrid processor systems provide a flexible platform for mapping data-parallel applications, while providing considerable speedup over software implementations. However, the overhead for reconfiguration presents a significant deterrent in ...
Run-time reconfigurable systems for digital signal processing applications: a survey

Today's digital signal processing (DSP) applications use computationally complex and/or adaptive algorithms and have stringent requirements in terms of speed, size, cost, power consumption, and throughput. Efficient hardware implementation techniques ...
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems

The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 3, Issue 2

May 2004

225 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/993396

Issue’s Table of Contents

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 May 2004

Published in TECS Volume 3, Issue 2

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

28
Total Citations
View Citations
1,947
Total Downloads

Downloads (Last 12 months)7
Downloads (Last 6 weeks)2

Reflects downloads up to 10 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Gong LDiessel O(2014)Simulation-based functional verification of dynamically reconfigurable systemsACM Transactions on Embedded Computing Systems10.1145/256004213:4(1-23)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2560042
Gong LDiessel OGong LDiessel O(2014)ConclusionsFunctional Verification of Dynamically Reconfigurable FPGA-based Systems10.1007/978-3-319-06838-1_7(151-155)Online publication date: 22-Jul-2014
https://doi.org/10.1007/978-3-319-06838-1_7
Gong LDiessel OGong LDiessel O(2014)Case StudiesFunctional Verification of Dynamically Reconfigurable FPGA-based Systems10.1007/978-3-319-06838-1_5(87-125)Online publication date: 22-Jul-2014
https://doi.org/10.1007/978-3-319-06838-1_5
Gong LDiessel OGong LDiessel O(2014)Getting Started with VerificationFunctional Verification of Dynamically Reconfigurable FPGA-based Systems10.1007/978-3-319-06838-1_4(65-86)Online publication date: 22-Jul-2014
https://doi.org/10.1007/978-3-319-06838-1_4
Gong LDiessel OGong LDiessel O(2014)Modeling ReconfigurationFunctional Verification of Dynamically Reconfigurable FPGA-based Systems10.1007/978-3-319-06838-1_3(41-64)Online publication date: 22-Jul-2014
https://doi.org/10.1007/978-3-319-06838-1_3
Gong LDiessel OGong LDiessel O(2014)Verification ChallengesFunctional Verification of Dynamically Reconfigurable FPGA-based Systems10.1007/978-3-319-06838-1_2(15-40)Online publication date: 22-Jul-2014
https://doi.org/10.1007/978-3-319-06838-1_2
Gong LDiessel OPaul JStechele W(2013)RTL Simulation of High Performance Dynamic ReconfigurationProceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum10.1109/IPDPSW.2013.79(106-113)Online publication date: 20-May-2013
https://dl.acm.org/doi/10.1109/IPDPSW.2013.79
Diessel O(2013)Opportunities and challenges for dynamic FPGA reconfiguration in electronic measurement and instrumentation2013 IEEE 11th International Conference on Electronic Measurement & Instruments10.1109/ICEMI.2013.6743028(258-263)Online publication date: Aug-2013
https://doi.org/10.1109/ICEMI.2013.6743028
Gong LDiessel OCompton KHutchings B(2012)Functionally verifying state saving and restoration in dynamically reconfigurable systemsProceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays10.1145/2145694.2145735(241-244)Online publication date: 22-Feb-2012
https://dl.acm.org/doi/10.1145/2145694.2145735
Silva MFerreira J(2012)Run-time generation of partial FPGA configurationsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2011.10.00158:1(24-37)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1016/j.sysarc.2011.10.001
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents