Article

Free access

The design of nectar: a network backplane for heterogeneous multicomputers

Authors:

Eric C. CoopermAuthors Info & Claims

ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systems

Pages 205 - 216

https://doi.org/10.1145/70082.68202

Published: 01 April 1989 Publication History

PDF eReader

Abstract

Nectar is a “network backplane” for use in heterogeneous multicomputers. The initial system consists of a star-shaped fiber-optic network with an aggregate bandwidth of 1.6 gigabits/second and a switching latency of 700 nanoseconds. The system can be scaled up by connecting hundreds of these networks together.

The Nectar architecture provides a flexible way to handle heterogeneity and task-level parallelism. A wide variety of machines can be connected as Nectar nodes and the Nectar system software allows applications to communicate at a high level. Protocol processing is off-loaded to powerful communication processors so that nodes do not have to support a suite of network protocols.

We have designed and built a prototype Nectar system that has been operational since November 1988. This paper presents the motivation and goals for Nectar and describes its hardware and software. The presentation emphasizes how the goals influenced the design decisions and led to the novel aspects of Nectar.

References

[1]

Marco Annaratone, Emmanuel Amould, Thomas Gross, H. T. Kung, Monica Lam, Onat Menzilcio~lu, and Jon A. Webb. The Warp computer: architecture, implementation and performance. IEEE Transactions on Computers, C-36(12):1523-1538, December 1987.]]

Digital Library

Google Scholar

[2]

William C. Athas and Charles L. Seitz. Multicomputers: message-passing concurrent computers. Computer, 21(8):9-24, August 1988.]]

Digital Library

Google Scholar

[3]

Luis-Felipe Cabrera, Edward Hunter, Michael J. Karels, and David A. Mosher. User-process communication performance in networks of computers. IEEE Transactions on Software Engineering, SE-14(i):3~ 53, lanuary 1988.]]

Digital Library

Google Scholar

[4]

David R, Cheriton, VMTP: Versatile Message Transaction Protocol. RFC 1045, Stanford University, February 1988.]]

Digital Library

Google Scholar

[5]

Greg Chesson. Protocol engine design. In Proceedings of the Sunm~r 1987 USENIX Conference, pages 209-215, June 1987.]]

Google Scholar

[6]

David D. Clark. The structuring of systems using upcalls. In Proceedings of the Tenth ACM Symposium on Operating Systems Principles, pages 171-180, ACM, December 1985.]]

Digital Library

Google Scholar

[7]

E. Clementi, $. Detrich, S. Chin, G. Corongiu, D. Folsom, D. Logan, R. Caltabiano, A. Carnevali, J. Helin, M. Russo, A. Gnuda, and P. Palarnidese. Large-scale computations on a scalar, vector and parallel "$upercomputer". In E. Clementi and S. Chin, editors, Structure and Dynamics of Nucleic Acids, Proteins and Membranes, pages 403- 450, Plenum Press, 1986.]]

Google Scholar

[8]

Eric C. Cooper and Richard P. Draves. C Threads. Technical Report CMU--CS-88-154, Computer Science Department, Carnegie Mellon University, June 1988.]]

Google Scholar

[9]

Allesandro Forin, Joseph Barrera, and Richard Sanzi. The shared memory server. In Winter USENIX Conference, Usenix, San Diego, lanuary 1989.]]

Google Scholar

[10]

iPSC/2 C Programmer's Reference Manual. Intel Corporation, March 1988.]]

Google Scholar

[11]

Hemant Kanakia and David R. Cheriton. The VMP network adaptor board (NAB): high-performance network communication for multiprocessors. In Proceedings of the SIGCOMM '88 Symposium on Communications Architectures and Protocols, pages 175-187, ACM, August 1988. Also published as Computer Communications Review, 18(4).]]

Digital Library

Google Scholar

[12]

Richard F. Rashid, Avadis Tevanian, Jr., Michael W. Young, David B. Golub, Robert V. Baron, David L. Black, William Bolosky, and Jonathan J. Chew. Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures. IEEE Transactions on Computers, C-37(8):896-908, August 1988.]]

Digital Library

Google Scholar

[13]

Alfred Z. Spector, Joshua I. Bloch, Dean S. Daniels, Richard P. Draves, Daniel J. Duchamp, Jeffrey L. Eppinger, Sherri G. Menees, and Dean S. Thompson. The Camelot project. Database Engineering, 9(4), December 1986. Also published as Technical Report CMU-CS-86-166, Computer Science Department, Carnegie Mellon University, November 1986.]]

Google Scholar

[14]

Milind Tambe, Dirk Kalp, Anoop Gupta, Charles Forgy, Brian Milnes, and Allen NeweI1. Soar/PSM-E: investigating match parallelism in a learning production system. In Proceedings of the ACM/SIGPLAN PPEALg 1988: Parallel Programming: Experience with Applications, Languages, and Systems, pages 146-161, ACM, July 1988. Also published as SIGPLAN Notices, 23(9).]]

Digital Library

Google Scholar

Cited By

View all

Kundu AXu GJi C(2014)Data Specific Ranking in CloudInternational Journal of Cloud Applications and Computing10.4018/ijcac.20141001034:4(32-41)Online publication date: 1-Oct-2014
https://dl.acm.org/doi/10.4018/ijcac.2014100103
Ishizaka MTsuchida MIdeguchi T(2007)Parallel processing scheme of the received data based on OSI protocolsElectronics and Communications in Japan (Part I: Communications)10.1002/ecja.441074110374:11(26-41)Online publication date: 23-Mar-2007
https://doi.org/10.1002/ecja.4410741103
Traw CSmith J(2006)Hardware/software organization of a high-performance ATM host interfaceIEEE Journal on Selected Areas in Communications10.1109/49.21501911:2(240-253)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/49.215019
Show More Cited By

Index Terms

The design of nectar: a network backplane for heterogeneous multicomputers

Recommendations

The design of nectar: a network backplane for heterogeneous multicomputers
Special issue: Proceedings of ASPLOS-III: the third international conference on architecture support for programming languages and operating systems

Nectar is a “network backplane” for use in heterogeneous multicomputers. The initial system consists of a star-shaped fiber-optic network with an aggregate bandwidth of 1.6 gigabits/second and a switching latency of 700 nanoseconds. The system can be ...
Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures
SBCCI '05: Proceedings of the 18th annual symposium on Integrated circuits and system design

Networks-on-chip (NoCs) are communication architecture alternatives for complex Systems-on-Chip (SoCs) designs, due to their high scalability and bandwidth. In this paper, we consider a heterogeneous NoC as an alternative to match performance and energy ...
Exploring heterogeneous NoC design space
ICCAD '11: Proceedings of the International Conference on Computer-Aided Design

The Network-on-Chip (NoC) plays a crucial role in designing low cost chip multiprocessors (CMPs) as the number of cores on a chip keeps increasing. However, buffers in NoC routers increase the cost of CMPs in terms of both area and power. Recently, ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systems

April 1989

303 pages

ISBN:0897913000

DOI:10.1145/70082

Chairman:
Joel Emer,
General Chair:
John Hennessy
Stanford University

ACM SIGARCH Computer Architecture News Volume 17, Issue 2
Special issue: Proceedings of ASPLOS-III: the third international conference on architecture support for programming languages and operating systems
April 1989
291 pages
ISSN:0163-5964
DOI:10.1145/68182
Editor:
Joel Emer
Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1989

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ASPLOS89

Sponsor:

ASPLOS89: Int'l Conference on Architecture Support for Programming Lang & Operating Systems

April 3 - 6, 1989

Massachusetts, Boston, USA

Acceptance Rates

Overall Acceptance Rate 535 of 2,713 submissions, 20%

Upcoming Conference

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

113
Total Citations
View Citations
489
Total Downloads

Downloads (Last 12 months)81
Downloads (Last 6 weeks)19

Reflects downloads up to 20 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Kundu AXu GJi C(2014)Data Specific Ranking in CloudInternational Journal of Cloud Applications and Computing10.4018/ijcac.20141001034:4(32-41)Online publication date: 1-Oct-2014
https://dl.acm.org/doi/10.4018/ijcac.2014100103
Ishizaka MTsuchida MIdeguchi T(2007)Parallel processing scheme of the received data based on OSI protocolsElectronics and Communications in Japan (Part I: Communications)10.1002/ecja.441074110374:11(26-41)Online publication date: 23-Mar-2007
https://doi.org/10.1002/ecja.4410741103
Traw CSmith J(2006)Hardware/software organization of a high-performance ATM host interfaceIEEE Journal on Selected Areas in Communications10.1109/49.21501911:2(240-253)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/49.215019
Davie B(2006)The architecture and implementation of a high-speed host interfaceIEEE Journal on Selected Areas in Communications10.1109/49.21501811:2(228-239)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/49.215018
Dinda PO'Hallaron DSubhlok JWebb JYang B(2005)Language and run-time support for network parallel computingLanguages and Compilers for Parallel Computing10.1007/BFb0014222(534-550)Online publication date: 9-Jun-2005
https://doi.org/10.1007/BFb0014222
Wu I(2005)Efficient parallel divide-and-conquer for a class of interconnection topologiesISA'91 Algorithms10.1007/3-540-54945-5_67(229-240)Online publication date: 1-Jun-2005
https://doi.org/10.1007/3-540-54945-5_67
Chien CKanade T(2005)Distributed quadtree processingDesign and Implementation of Large Spatial Databases10.1007/3-540-52208-5_29(213-232)Online publication date: 31-May-2005
https://doi.org/10.1007/3-540-52208-5_29
Jaganathan RUnderwood KSass RMcGraw J(2003)A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NICProceedings of the 2003 ACM/IEEE conference on Supercomputing10.1145/1048935.1050173Online publication date: 15-Nov-2003
https://dl.acm.org/doi/10.1145/1048935.1050173
Braun FLockwood JWaldvogel M(2002)Protocol Wrappers for Layered Network Packet Processing in Reconfigurable HardwareIEEE Micro10.1109/40.98869122:1(66-74)Online publication date: 1-Jan-2002
https://dl.acm.org/doi/10.1109/40.988691
Braun FLockwood JWaldvogel M(2001)Layered protocol wrappers for Internet packet processing in reconfigurable hardwareHOT 9 Interconnects. Symposium on High Performance Interconnects10.1109/HIS.2001.946699(93-97)Online publication date: 2001
https://doi.org/10.1109/HIS.2001.946699
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

The design of nectar: a network backplane for heterogeneous multicomputers

Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures

Exploring heterogeneous NoC design space