Article

Static noise analysis with noise windows

Authors:

Ken Tseng,

Vinod KariatAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 864 - 868

https://doi.org/10.1145/775832.776049

Published: 02 June 2003 Publication History

Get Access

Abstract

As processing technology scales down to the nanometer regime, capacitive crosstalk is having an increasingly adverse effect on circuit functionality, leading to increasing number of chip failures. In this paper, we propose mapping the static crosstalk functional noise problem into the well understood static timing problem. The key differences between static noise and static timing analyses, namely the injection of noise, accurate noise window propagation and register sensitive window computation are the contributions of this work. We demonstrate the effectiveness of this approach in two industrial designs by achieving 5X reduction in functional noise failures over noise propagation without considering timing of the composite noise pulse envelope, and 30X reduction in functional noise failures over net based noise failure metrics.

References

[1]

K. L. Shepard and V. Narayanan, "Noise in Deep Submicron Digital Design", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 524--531, November 1996.

Digital Library

Google Scholar

[2]

P.Chen, K.Keutzer, "Towards True Crosstalk Noise Analysis", International Conference on Computer-Aided Design, pp.132--137, 1999.

Digital Library

Google Scholar

[3]

Xiao, T., Marek-Sadowska, M. "Worst delay estimation in crosstalk aware static timing analysis", International Conference on Computer Design, 2000, pp. 115--120.

Digital Library

Google Scholar

[4]

Scheffer, L. "What is the appropriate model for crosstalk control?" 13th Symposium on Integrated Circuits and Systems Design, 2000, pp. 315--320.

Digital Library

Google Scholar

[5]

C. J. Alpert, A. Devgan, S. T. Quay, "Buffer Insertion for Noise and Delay Optimization", IEEE Transactions on Computer-Aided Design, pp. 1633--1645, November 1999.

Digital Library

Google Scholar

[6]

Hui Chen, L.; Marek-Sadowska, M., "Aggressor alignment for worst-case crosstalk noise", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Volume: 20 Issue: 5, May 2001, pp. 612--621.

Digital Library

Google Scholar

[7]

Shepard, K.L.; Chou, K. "Cell characterization for noise stability", Custom Integrated Circuits Conference, 2000, pp. 91--94.

Google Scholar

[8]

CeltIC User Guide, Cadence Design Systems, 2002.

Google Scholar

[9]

PacifIC User Guide, Cadence Design Systems, 2002.

Google Scholar

[10]

Levy, R.; Blaauw, D.; Braca, G.; Dasgupta, A.; Grinshpon, A.; Chanhee Oh; Orshav, B.; Sirichotiyakul, S.; Zolotov, V. "ClariNet: a noise analysis tool for deep submicron design", Design Automation Conference, 2000, pp. 233--238

Digital Library

Google Scholar

[11]

Zolotov, V.; Blaauw, D.; Sirichotiyakul, S.; Becer, M.; Oh, C; Panda, R; Grinshpon, A.; Levy, R.; "Noise Propagation and Failure Criteria for VLSI Designs", International Conference on Computer Aided Design, pp. 587--594, 2002.

Digital Library

Google Scholar

[12]

Bryant, R. E., "Extraction of gate level models from transistor circuits by four-valued symbolic analysis", International Conference on Computer Aided Design, pp. 350--353, 1991.

Crossref

Google Scholar

[13]

Kuehlmann, A., Srinivasan, A., LaPotin, D. P., "Verity - A formal verification program for custom CMOS circuits", IBM J. Res. Development, Vol. 39, No. 1/2, pp. 149--165, Jan/Mar 1995.

Digital Library

Google Scholar

[14]

Bryant, R. E., "Graph-based algorithm for boolean function manipulation", IEEE Trans. Computers, Vol. 35, No. 8, pp. 677--691, Aug. 1986.

Digital Library

Google Scholar

Cited By

View all

Zolotov VFeldmann P(2015)Variation aware cross-talk aggressor alignment by mixed integer linear programmingProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744924(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744924
Zejda JDing L(2006)TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro BlocksProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.131(147-152)Online publication date: 27-Mar-2006
https://dl.acm.org/doi/10.1109/ISQED.2006.131
Gyure AKasnavi ALo STehrani PShu WShahram MWang JZedja J(2005)Noise Library Characterization for Large Capacity Static Noise Analysis ToolsProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.85(28-34)Online publication date: 21-Mar-2005
https://dl.acm.org/doi/10.1109/ISQED.2005.85
Show More Cited By

Index Terms

Static noise analysis with noise windows
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

Recommendations

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: ...
Dynamic Noise Analysis with Capacitive and Inductive Coupling
ASP-DAC '02: Proceedings of the 2002 Asia and South Pacific Design Automation Conference

In this paper we propose a dynamic noise model to verify functional failures due to crosstalk in high-speed circuits. Conventional DC noise analysis produces pessimistic results because it ignores the fact that a gate acts as a low-pass filter. In ...
A complete methodology for an accurate static noise analysis
GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

In signal integrity analysis, the joint effect of propagated noise through library cells, and of the noise injected on a quiet net by neighboring switching nets through coupling capacitances, must be considered in order to accurately estimate the ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2003

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

DAC03

Sponsor:

SIGDA

DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

Acceptance Rates

DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
577
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 01 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Zolotov VFeldmann P(2015)Variation aware cross-talk aggressor alignment by mixed integer linear programmingProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744924(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744924
Zejda JDing L(2006)TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro BlocksProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.131(147-152)Online publication date: 27-Mar-2006
https://dl.acm.org/doi/10.1109/ISQED.2006.131
Gyure AKasnavi ALo STehrani PShu WShahram MWang JZedja J(2005)Noise Library Characterization for Large Capacity Static Noise Analysis ToolsProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.85(28-34)Online publication date: 21-Mar-2005
https://dl.acm.org/doi/10.1109/ISQED.2005.85
Kanj RLehner TAgrawal BRosenbaum EMalik SFix LKahng A(2004)Noise characterization of static CMOS gatesProceedings of the 41st annual Design Automation Conference10.1145/996566.996803(888-893)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996803
Phadoongsidhi MSaluja K(2004)Static timing analysis of irreversible crosstalk noise pulse faults17th International Conference on VLSI Design. Proceedings.10.1109/ICVD.2004.1260961(437-442)Online publication date: 2004
https://doi.org/10.1109/ICVD.2004.1260961

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Crosstalk noise reduction in synthesized digital logic circuits

Dynamic Noise Analysis with Capacitive and Inductive Coupling

A complete methodology for an accurate static noise analysis