Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing
Article No.: 8, Pages 1 - 17
Abstract
Spin-Transfer-Torque RAM (STTRAM) is a promising technology for high-density on-chip cache due to low standby power and high speed. However, the process variation of the Magnetic Tunnel Junction (MTJ) and access transistor poses a serious challenge to sensing. Nondestructive sensing suffers from reference resistance variation, whereas destructive sensing suffers from failures due to unoptimized selection of data and reference currents. Furthermore, the sense speed is tightly coupled with the reference/data current requirement. In this work, we study the process variation effect on a self-reference sensing scheme to eliminate bit-to-bit process variation in MTJ resistance. Read current modulation is proposed to overcome the failures due to process variation. Simulation results reveal <0.01% failures at the cost of 9ns sense time and 190uW power consumption.
References
[1]
ASU. Predictive Technology Model. 2008. Retrieved from http://www.asu.edu/∼ptm.
[2]
K.S. Au Edward, Wing-Hung Ki, Wai Ho Mow, Silas T. Hung, and Catherine Y. Wong. 2004. A novel current-mode sensing scheme for magnetic tunnel junction MRAM. IEEE Transactions on Magnetics 40, 2 (2004), 483--488.
[3]
Lee Dongsoo and Kaushik Roy. 2014. Energy-delay optimization of the STT MRAM write operation under process variations. In IEEE Transactions on Nanotechnology 13, 4 (2014), 714--723.
[4]
Y. Emre et al. 2012. Enhancing the reliability of STT-RAM through circuit and system level techniques. In SiPS, 2012.
[5]
X. Fong, S. H. Choday, P. Georgios, C. Augustine, and K. Roy. 2013. SPICE Models for Magnetic Tunnel Junctions Based on Monodomain Approximation. Retrieved from https://nanohub.org/resources/19048.
[6]
D. Halupka et al. 2010. Negative-resistance read and write schemes for STT-MRAM in 0.13 μm CMOS. In ISSCC, 2010.
[7]
M. Hosomi et al. 2005. A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. In IEDM, 2005.
[8]
Gitae Jeong, Wooyoung Cho, Sujin Ahn, Hongsik Jeong, Gwanhyeob Koh, Youngnam Hwang, and Kinam Kim. 2003. A 0.24-/spl mu/m 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme. In IEEE Journal of Solid-State Circuits 38, 11 (2003), 1906--1910.
[9]
L. Jing et al. 2008. Variation-tolerant spin-torque transfer (STT) MRAM array for yield enhancement. In IEEE Custom Integrated Circuits Conference, 2008 (CICC’08). IEEE.
[10]
K. Jisu et al. 2012. A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM). IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, 1 (2012), 181--186.
[11]
K. Jisu et al. 2014. STT-MRAM sensing circuit with self-body biasing in deep submicron technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, 7 (2014), 1630--1634.
[12]
A. Junwhan, S. Yoo, and K. Choi. 2014. DASCA: Dead write prediction assisted STT-RAM cache architecture. In 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA'14). IEEE.
[13]
A. Khouzani, H. Y. Xue, C. Yang, and A. Pandurangi. 2014. Prolonging PCM lifetime through energy-efficient, segment-aware, and wear-resistant page allocation. In Proceedings of the 2014 International Symposium on Low Power Electronics and Design. ACM, 327--330.
[14]
Y. Kim et al. 2012. Write-optimized reliable design of STT MRAM. In ISLPED, 2012.
[15]
D. Lee et al. 2012. High-performance low-energy STT MRAM based on balanced write scheme. In ISLPED, 2012.
[16]
J. Li et al. 2010. Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. In TVLSI, 2010.
[17]
Marcel J. M. Pelgrom, Aad C. J. Duinmaijer, and Anton P. G. Welbers. 1989. Matching properties of MOS transistors. IEEE Journal of Solid-State Circuits 24, 5 (1989): 1433--1439.
[18]
Bushnell Michael and Vishwani Agrawal. 2004. Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. 17. Springer Science 8 Business Media.
[19]
I. Mohsen, S. Patil, and T. Rosing. 2016. Low power data-aware STT-RAM based hybrid ache architecture. In 2016 17th International Symposium on Quality Electronic Design (ISQED’16). IEEE.
[20]
I. Mohsen et al. 2016. A low-power hybrid magnetic cache architecture exploiting narrow-width values. In 2006 5th Non-Volatile Memory Systems and Applications Symposium (NVMSA’16). IEEE.
[21]
Zand Ramtin, Arman Roohi, and Ronald F. DeMara. 2017. Energy-efficient and process-variation-resilient write circuit schemes for spin hall effect MRAM Device. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[22]
M. Rasquinha et al. 2010. An energy efficient cache design using spin torque transfer (stt) ram. In ISLPED, 2010.
[23]
F. Ren et al. 2012. A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs). In ISQED, 2012.
[24]
J. Seong-Ook et al. 2011. Balancing a signal margin of a resistance based memory circuit. U.S. Patent 7, 889, 585. Feb. 15, 2011.
[25]
M. Seyedhamidreza and S. Ghosh. 2014. Simultaneous sizing, reference voltage and clamp voltage biasing for robustness, self-calibration and testability of STTRAM arrays. In Proceedings of the 51st Annual Design Automation Conference. ACM, 1--2.
[26]
M. Seyedhamidreza et al. 2015. A novel slope detection technique for robust STTRAM sensing. In 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’15). IEEE, 7--12.
[27]
C. W. Smullen et al. 2011. Relaxing non-volatility for fast and energy-efficient STT-RAM caches. In HPCA, 2011.
[28]
Jee-Hwan Song, Jisu Kim, Seung H. Kang, Sei-Seung Yoon, and Seong-Ook Jung. 2011. Sensing margin trend with technology scaling in MRAM. In International Journal of Circuit Theory and Applications 39, 3 (2011), 313--325.
[29]
C. Xu et al. 2010. Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. In ICCAD, 2010.
[30]
Z. Yaojun et al. 2011. STT-RAM cell optimization considering MTJ and CMOS variations. IEEE Transactions on Magnetics 47, 10 (2011), 2962--2965.
[31]
C. Yiran et al. 2012. A 130 nm 1.2 V/3.3 V 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme. IEEE Journal of Solid-State Circuits 47, 2 (2012), 560--573.
[32]
P. Zhou et al. 2009. Energy reduction for STT-RAM using early write termination. In ICCAD, 2009.
Index Terms
- Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing
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Publication History
Published: 25 October 2017
Accepted: 01 August 2017
Revised: 01 May 2017
Received: 01 January 2016
Published in JETC Volume 14, Issue 1
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