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Maximizing performance by retiming and clock skew scheduling

Authors:

Xun Liu,

Marios C. Papaefthymiou,

Eby G. FriedmanAuthors Info & Claims

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Pages 231 - 236

https://doi.org/10.1145/309847.309919

Published: 01 June 1999 Publication History

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Cited By

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Jayakrishnan MChang AKim T(2018)Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time ApplicationsJournal of Low Power Electronics and Applications10.3390/jlpea80200098:2(9)Online publication date: 21-Mar-2018
https://doi.org/10.3390/jlpea8020009
Kim JKim T(2017)Adjustable Delay Buffer Allocation under Useful Clock Skew SchedulingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.259721336:4(641-654)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2597213
Roy SPan DMattheakis PColyer PMasse-Navette LRibet PJones ALi HCoskun AMargala M(2015)Skew Bounded Buffer Tree Resynthesis For Clock Power OptimizationProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742119(87-90)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742119
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Index Terms

Maximizing performance by retiming and clock skew scheduling
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design
2. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Process management

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Published In

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1999

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DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference

June 21 - 25, 1999

Louisiana, New Orleans, USA

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DAC '99 Paper Acceptance Rate 154 of 451 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Jayakrishnan MChang AKim T(2018)Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time ApplicationsJournal of Low Power Electronics and Applications10.3390/jlpea80200098:2(9)Online publication date: 21-Mar-2018
https://doi.org/10.3390/jlpea8020009
Kim JKim T(2017)Adjustable Delay Buffer Allocation under Useful Clock Skew SchedulingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.259721336:4(641-654)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2597213
Roy SPan DMattheakis PColyer PMasse-Navette LRibet PJones ALi HCoskun AMargala M(2015)Skew Bounded Buffer Tree Resynthesis For Clock Power OptimizationProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742119(87-90)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742119
Roy SMattheakis PMasse-Navette LPan DSze CDavoodi A(2014)Clock tree resynthesis for multi-corner multi-mode timing closureProceedings of the 2014 on International symposium on physical design10.1145/2560519.2560524(69-76)Online publication date: 30-Mar-2014
https://dl.acm.org/doi/10.1145/2560519.2560524
Kondratyev ALavagno LMeyer MWatanabe YRosenstiel WMacii E(2012)Exploiting area/delay tradeoffs in high-level synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492963(1024-1029)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492963
Chou HYu HChang SPhillips JHu AGraeb H(2011)Useful-skew clock optimization for multi-power mode designsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132470(647-650)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132470
Joshi VBlaauw DSylvester DGielen G(2007)Soft-edge flip-flops for improved timing yieldProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326214(667-673)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326214
Nawale VChen THassoun S(2006)Optimal useful clock skew scheduling in the presence of variations using robust ILP formulationsProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233508(27-32)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233508
Saitoh MAzuma MTakahashi A(2001)Clustering based fast clock scheduling for light clock-treeProceedings of the conference on Design, automation and test in Europe10.5555/367072.367198(240-245)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367198
Toyonaga MKurokawa KYasui TTakahashi AWiesel MHill D(2000)A practical clock tree synthesis for semi-synchronous circuitsProceedings of the 2000 international symposium on Physical design10.1145/332357.332393(159-164)Online publication date: 1-May-2000
https://dl.acm.org/doi/10.1145/332357.332393

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Delay insertion method in clock skew scheduling

Pulse width allocation and clock skew scheduling: optimizing sequential circuits based on pulsed latches

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks