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Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB

Authors:

Nagendra Gulur,

Lizy K. JohnAuthors Info & Claims

ISCA '17: Proceedings of the 44th Annual International Symposium on Computer Architecture

Pages 469 - 480

https://doi.org/10.1145/3079856.3080210

Published: 24 June 2017 Publication History

Abstract

With increasing deployment of virtual machines for cloud services and server applications, memory address translation overheads in virtualized environments have received great attention. In the radix-4 type of page tables used in x86 architectures, a TLB-miss necessitates up to 24 memory references for one guest to host translation. While dedicated page walk caches and such recent enhancements eliminate many of these memory references, our measurements on the Intel Skylake processors indicate that many programs in virtualized mode of execution still spend hundreds of cycles for translations that do not hit in the TLBs.

This paper presents an innovative scheme to reduce the cost of address translations by using a very large Translation Lookaside Buffer that is part of memory, the POM-TLB. In the POM-TLB, only one access is required instead of up to 24 accesses required in commonly used 2D walks with radix-4 type of page tables. Even if many of the 24 accesses may hit in the page walk caches, the aggregated cost of the many hits plus the overhead of occasional misses from page walk caches still exceeds the cost of one access to the POM-TLB. Since the POM-TLB is part of the memory space, TLB entries (as opposed to multiple page table entries) can be cached in large L2 and L3 data caches, yielding significant benefits. Through detailed evaluation running SPEC, PARSEC and graph workloads, we demonstrate that the proposed POM-TLB improves performance by approximately 10% on average. The improvement is more than 16% for 5 of the benchmarks. It is further seen that a POM-TLB of 16MB size can eliminate nearly all TLB misses in 8-core systems.

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Gao BKang QTee HChu KSanaee AJevdjic DBagchi SZhang Y(2024)Scalable and effective page-table and TLB management on NUMA systemsProceedings of the 2024 USENIX Conference on Usenix Annual Technical Conference10.5555/3691992.3692020(445-461)Online publication date: 10-Jul-2024
https://dl.acm.org/doi/10.5555/3691992.3692020
Zhang JJia WChai SLiu PKim JXu TTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)Direct Memory Translation for Virtualized CloudsProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640358(287-304)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620665.3640358
Ham HHong JPark GShin YWoo OYang WBae JPark ESung HLim EKim G(2024)Low-Overhead General-Purpose Near-Data Processing in CXL Memory Expanders2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00051(594-611)Online publication date: 2-Nov-2024
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Index Terms

Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems

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cover image ACM Conferences

ISCA '17: Proceedings of the 44th Annual International Symposium on Computer Architecture

June 2017

736 pages

ISBN:9781450348928

DOI:10.1145/3079856

ACM SIGARCH Computer Architecture News Volume 45, Issue 2
ISCA'17
May 2017
715 pages
ISSN:0163-5964
DOI:10.1145/3140659
Editor:
Babak Falsafi
Interim
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Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 24 June 2017

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ISCA '17: The 44th Annual International Symposium on Computer Architecture

June 24 - 28, 2017

ON, Toronto, Canada

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ISCA '17 Paper Acceptance Rate 54 of 322 submissions, 17%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

Gao BKang QTee HChu KSanaee AJevdjic DBagchi SZhang Y(2024)Scalable and effective page-table and TLB management on NUMA systemsProceedings of the 2024 USENIX Conference on Usenix Annual Technical Conference10.5555/3691992.3692020(445-461)Online publication date: 10-Jul-2024
https://dl.acm.org/doi/10.5555/3691992.3692020
Zhang JJia WChai SLiu PKim JXu TTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)Direct Memory Translation for Virtualized CloudsProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640358(287-304)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620665.3640358
Ham HHong JPark GShin YWoo OYang WBae JPark ESung HLim EKim G(2024)Low-Overhead General-Purpose Near-Data Processing in CXL Memory Expanders2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00051(594-611)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00051
Psomadakis SAlverti CKarakostas VKatsakioris CSiakavaras DNikas KGoumas GKoziris N(2024)Elastic Translations: Fast Virtual Memory with Multiple Translation Sizes2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00012(17-35)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00012
Chen DTong DYang CYi JCheng X(2023)FlexPointer: Fast Address Translation Based on Range TLB and Tagged PointersACM Transactions on Architecture and Code Optimization10.1145/357985420:2(1-24)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1145/3579854
Sá BValente LMartins JRossi DBenini LPinto S(2023)CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space ExplorationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.330283731:11(1713-1726)Online publication date: Nov-2023
https://doi.org/10.1109/TVLSI.2023.3302837
Stojkovic JMantri NSkarlatos DXu TTorrellas J(2023)Memory-Efficient Hashed Page Tables2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071061(1221-1235)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071061
Fatima ALiu SSeemakhupt KAusavarungnirun RKhan S(2023)vPIM: Efficient Virtual Address Translation for Scalable Processing-in-Memory Architectures2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247745(1-6)Online publication date: 9-Jul-2023
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AOYAMA NYAMADA H(2022)Comparison of Value- and Reference-Based Memory Page Compaction in Virtualized SystemsIEICE Transactions on Information and Systems10.1587/transinf.2022EDP7027E105.D:12(2075-2084)Online publication date: 1-Dec-2022
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Park CVougioukas ISandberg ABlack-Schaffer DFalsafi BFerdman MLu SWenisch T(2022)Every walk’s a hit: making page walks single-access cache hitsProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507718(128-141)Online publication date: 28-Feb-2022
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