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Cited By

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Pasricha SDutt N(2008)On-Chip Communication Architecture Refinement and Interface SynthesisOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00009-8(341-366)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00009-8
Chu YGade ABhaduri A(2006)A low-power cache scheme for embedded computingJournal of Embedded Computing10.5555/1370998.13710062:2(261-269)Online publication date: 1-Apr-2006
https://dl.acm.org/doi/10.5555/1370998.1371006
Ghosh AGivargis T(2003)Cache Optimization For Embedded Processor CoresProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009912Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009912
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Index Terms

The case for a configure-and-execute paradigm
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign

March 1999

216 pages

ISBN:1581131321

DOI:10.1145/301177

Chairmen:
Ahmed Amine Jerraya
TIMA Lab, France
,
Luciano Lavagno
Politecnico di Torino, Turin, Italy
,
Frank Vahid
Univ. of California, Riverside

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 March 1999

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CODES99: International Conference on Hardware/Software Codesign

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CODES '99 Paper Acceptance Rate 40 of 98 submissions, 41%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

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Pasricha SDutt N(2008)On-Chip Communication Architecture Refinement and Interface SynthesisOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00009-8(341-366)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00009-8
Chu YGade ABhaduri A(2006)A low-power cache scheme for embedded computingJournal of Embedded Computing10.5555/1370998.13710062:2(261-269)Online publication date: 1-Apr-2006
https://dl.acm.org/doi/10.5555/1370998.1371006
Ghosh AGivargis T(2003)Cache Optimization For Embedded Processor CoresProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009912Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009912
Ghosh AGivargis T(2003)Analytical Design Space Exploration of Caches for Embedded SystemsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022799Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022799
Givargis TGetreu IFix LLavagno L(2003)Improved indexing for cache miss reduction in embedded systemsProceedings of the 40th annual Design Automation Conference10.1145/775832.776052(875-880)Online publication date: 2-Jun-2003
https://dl.acm.org/doi/10.1145/775832.776052
Vermeulen FCatthoor FNachtergaele LVerkest DDe Man H(2003)Power-efficient flexible processor architecture for embedded applicationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81077911:3(376-385)Online publication date: 1-Jun-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.810779
Northern JShanblatt M(2003)An evolutionary approach to configuring an embedded system based on power consumptionThe 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.10.1109/IWSOC.2003.1213035(201-204)Online publication date: 2003
https://doi.org/10.1109/IWSOC.2003.1213035
Ascia GCatania VPalesi M(2003)Tuning Methodologies for Parameterized Systems DesignSystem-on-Chip for Real-Time Applications10.1007/978-1-4615-0351-4_8(71-82)Online publication date: 2003
https://doi.org/10.1007/978-1-4615-0351-4_8
Palesi G(2002)A Framework for Design Space Exploration of Parameterized VLSI SystemsProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835448Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835448
Ascia GCatania VPalesi M(2002)Design space exploration methodologies for IP-based system-on-a-chip2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)10.1109/ISCAS.2002.1011000(II-364-II-367)Online publication date: 2002
https://doi.org/10.1109/ISCAS.2002.1011000
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Prefetching for improved bus wrapper performance in cores

A communication-theoretic design paradigm for reliable SOCs

Providing cost-effective on-chip network bandwidth in GPGPUs