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Power-efficient flexible processor architecture for embedded applications

Published: 01 June 2003 Publication History

Abstract

In the design of embedded systems, a processor architecture is a tradeoff between energy consumption, area, speed, design time, and flexibility to cope with future design changes. New versions in a product generation may require small design changes in any part of the design. We propose a novel processor architecture concept, which provides the flexibility needed in practice at a reduced power and performance cost compared to a fully programmable processor. The crucial element is a novel protocol combining an efficient, customized component with a flexible processor into a hybrid architecture.

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  • (2004)Customisable EPIC ProcessorProceedings of the conference on Design, automation and test in Europe - Volume 310.5555/968880.969248Online publication date: 16-Feb-2004

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 11, Issue 3
Special section on the 2001 international conference on computer design (ICCD)
June 2003
223 pages

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IEEE Educational Activities Department

United States

Publication History

Published: 01 June 2003

Author Tags

  1. configurable
  2. low-power design
  3. memory
  4. performance tradeoffs
  5. system architecture
  6. system level

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  • (2004)Customisable EPIC ProcessorProceedings of the conference on Design, automation and test in Europe - Volume 310.5555/968880.969248Online publication date: 16-Feb-2004

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