A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration

Partial dynamic reconfiguration of FPGAs can be used to implement complex applications using the concept of virtual hardware. In this work we have used partial dynamic reconfiguration to implement a JPEG decoder with reduced area. The image decoding ...

Despite the possibility to execute several hardware tasks in parallel on an FPGA, partial reconfiguration is sequential. There exist only one reconfiguration port which is used exclusively during the reconfiguration of a task. Single processor ...

This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard ...