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Decoupling processor and memory hierarchy simulators for efficient design space exploration

Published: 23 June 2022 Publication History

Abstract

Virtual prototyping is typically used for HW/SW co-design and architectural exploration. Due to the increasing design complexity and tight time-to-market, virtual prototyping platforms should achieve fast simulation speed while keeping model accuracy reasonable. Yet, the simulation speed decreases as the target design complexity increases. This paper presents a simulation approach based on decoupling processor emulation and memory hierarchy simulation for the purpose of efficiency. Our approach reduces the overhead of simulating complex memory hierarchies without jeopardizing the accuracy of the performance evaluation results. Experiments show a significant improvement in simulation speed with a good level of accuracy compared to sequential simulation.

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  • (2024)AI-based estimation of embedded software execution cycles in host-compiled simulation2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)10.1109/DCIS62603.2024.10769196(1-6)Online publication date: 13-Nov-2024
  • (2024)Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPCArchitecture of Computing Systems10.1007/978-3-031-66146-4_17(251-265)Online publication date: 1-Aug-2024
  • (2023)A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors2023 26th Euromicro Conference on Digital System Design (DSD)10.1109/DSD60849.2023.00108(756-763)Online publication date: 6-Sep-2023
  1. Decoupling processor and memory hierarchy simulators for efficient design space exploration

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    cover image ACM Other conferences
    DroneSE and RAPIDO: System Engineering for constrained embedded systems
    January 2022
    58 pages
    ISBN:9781450395663
    DOI:10.1145/3522784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 23 June 2022

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    • H2020 European Processor Initiative

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    View all
    • (2024)AI-based estimation of embedded software execution cycles in host-compiled simulation2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)10.1109/DCIS62603.2024.10769196(1-6)Online publication date: 13-Nov-2024
    • (2024)Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPCArchitecture of Computing Systems10.1007/978-3-031-66146-4_17(251-265)Online publication date: 1-Aug-2024
    • (2023)A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors2023 26th Euromicro Conference on Digital System Design (DSD)10.1109/DSD60849.2023.00108(756-763)Online publication date: 6-Sep-2023

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