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Lx: a technology platform for customizable VLIW embedded processing

Authors:

Paolo Faraboschi,

Geoffrey Brown,

Joseph A. Fisher,

Giuseppe Desoli,

Fred HomewoodAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 28, Issue 2

Pages 203 - 213

https://doi.org/10.1145/342001.339682

Published: 01 May 2000 Publication History

Abstract

Lx is a scalable and customizable VLIW processor technology platform designed by Hewlett-Packard and STMicroelectronics that allows variations in instruction issue width, the number and capabilities of structures and the processor instruction set. For Lx we developed the architecture and software from the beginning to support both scalability (variable numbers of identical processing resources) and customizability (special purpose resources).

In this paper we consider the following issues. When is customization or scaling beneficial? How can one determine the right degree of customization or scaling for a particular application domain? What architectural compromises were made in the Lx project to contain the complexity inherent in a customizable and scalable processor family?

The experiments described in the paper show that specialization for an application domain is effective, yielding large gains in price/performance ratio. We also show how scaling machine resources scales performance, although not uniformly across all applications. Finally we show that customization on an application-by-application basis is today still very dangerous and much remains to be done for it to become a viable solution.

References

[1]

Colwell, R., O'Donnell, J., Papworth, D., and Rodman, P. "Instruction Storage Method with a Compressed Format using a Mask Word", U.S. Patent 5057837, Oct. 1991.

[2]

Colwell, R. P., Nix, R. P., O'Donnell, J. J., Papworth, D. B., and Rodman, P.K. A VLIW Architecture for a Trace Scheduling Compiler. In Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems, pages pages 180-192. ACM. 1987.

Digital Library

[3]

Faraboschi, P., Fisher, J. and Desoli, G Clustered Instruction-Level Parallel Processors. Hewlett-Packard Technical Report. HPL-98-204, 1998.

[4]

Fisher, J., Faraboschi, P., and Desoli, G. "Custom-Fit Processors: Letting Applications Define Architectures". In Proc. 30th Annual International Symposium on Microarchitecture (MICRO30), Paris, France, December 1996.

Digital Library

[5]

Fisher, J. "Trace Scheduling: A Technique for Global Microcode Compaction". IEEE Trans. on Computers, C- 30(7):478-490. 1981.

Digital Library

[6]

IBM Corp. "CodePack Compression for PowerPC". Available as: http://www.chips.ibm.com/products/powerpc/ cores/cdpak.html

[7]

Lowney, P.G. et al. (1993). "The Multiflow Trace Scheduling Compiler". The Journal of Supercomputing, 7(1/2):51-142.

Digital Library

[8]

Raik-Allen G. "ARC Cores rides platform divergence trend". Red Herring, June 1999. Available as http://www. redherring.com/insider/1999/0604/vcarccores.html

[9]

Rau B., Yen D., Yen W., and Towle R., "The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs," IEEE Computer, January 1989, pp. 12-35.

Digital Library

[10]

Schneier B. "Applied Cryptography (Second Edition). Protocols, Algorithms and Source Code in C". John Wiley and Sons. 1996.

Digital Library

[11]

Sharangpani H. "Intel~ Itanium Processor Microarchitecture Overview". Microprocessor Forum. 1999. Available as: http ://developer.intel.com/design/ia-64/architecture.htm

[12]

Slavenburg G, Rathnam S., Dijkstra H, "The TriMedia TM- 1 PCI VLIW Media Processor", Hot Chips 8, August 1996.

[13]

StarCore Alliance (Motorola Semiconductors and Lucent Technologies). Leadership in DSP Technology for Communications Applications. Available as: http://www. starcore-dsp.com/files/S C 140pres.pdf

[14]

Tensilica Inc., "Application Specific Microprocessor Solutions (Data Sheet for Xtensa V1)", 1998. Available as: http ://www.tensilica.com/datasheet.pdf

[15]

Texas Instruments Inc. "TMS320C6000: a High Performance DSP Platform". Available as: http://www.ti.com/ sc/docs/products/dsp/c6000/index.htm

[16]

Wolfe, A. and Chanin, A., "Executing Compressed Programs on An Embedded RISC Architecture", In Proceedings of the 25th Annual International Symposium on Microarchitecture, pages 81-91, Portland, Oregon

Digital Library

Cited By

Dupont de Dinechin B(2021)SSA Form and Code GenerationSSA-based Compiler Design10.1007/978-3-030-80515-9_18(243-256)Online publication date: 12-Jun-2021
https://doi.org/10.1007/978-3-030-80515-9_18
Şuşu A(2020)A Vector-Length Agnostic Compiler for the Connex-S Accelerator with Scratchpad MemoryACM Transactions on Embedded Computing Systems10.1145/340653619:6(1-30)Online publication date: 3-Oct-2020
https://dl.acm.org/doi/10.1145/3406536
Jost TNazar GCarro L(2020)SoMMA: A software-managed memory architecture for multi-issue processorsMicroprocessors and Microsystems10.1016/j.micpro.2020.10313977(103139)Online publication date: Sep-2020
https://doi.org/10.1016/j.micpro.2020.103139
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Index Terms

Lx: a technology platform for customizable VLIW embedded processing
1. Computer systems organization

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 28, Issue 2

Special Issue: Proceedings of the 27th annual international symposium on Computer architecture (ISCA '00)

May 2000

325 pages

ISSN:0163-5964

DOI:10.1145/342001

Chairmen:
Alan Berenbaum
Lucent Technologies, Berkeley Heights, NJ
,
Joel Emer
Compaq Computer Corp., Palo Alto, CA

Issue’s Table of Contents

ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture
June 2000
327 pages
ISBN:1581132328
DOI:10.1145/339647
Chairmen:
Alan Berenbaum
Lucent Technologies
,
Joel Emer
Compaq Computer Corp.

Copyright © 2000 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 2000

Published in SIGARCH Volume 28, Issue 2

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Cited By

Dupont de Dinechin B(2021)SSA Form and Code GenerationSSA-based Compiler Design10.1007/978-3-030-80515-9_18(243-256)Online publication date: 12-Jun-2021
https://doi.org/10.1007/978-3-030-80515-9_18
Şuşu A(2020)A Vector-Length Agnostic Compiler for the Connex-S Accelerator with Scratchpad MemoryACM Transactions on Embedded Computing Systems10.1145/340653619:6(1-30)Online publication date: 3-Oct-2020
https://dl.acm.org/doi/10.1145/3406536
Jost TNazar GCarro L(2020)SoMMA: A software-managed memory architecture for multi-issue processorsMicroprocessors and Microsystems10.1016/j.micpro.2020.10313977(103139)Online publication date: Sep-2020
https://doi.org/10.1016/j.micpro.2020.103139
Ashouri AKillian WCavazos JPalermo GSilvano C(2018)A Survey on Compiler Autotuning using Machine LearningACM Computing Surveys10.1145/319797851:5(1-42)Online publication date: 18-Sep-2018
https://doi.org/10.1145/3197978
Ahmadi MZadkhosh E(2016)A customized and reconfigurable VLIW-based packet classifier on ρ-VEXJournal of High Speed Networks10.3233/JHS-16054122:3(177-192)Online publication date: 2-Jun-2016
https://doi.org/10.3233/JHS-160541
Wu IShann JHsu WChung C(2014)Extended Instruction Exploration for Multiple-Issue ArchitecturesACM Transactions on Embedded Computing Systems10.1145/256003913:4(1-28)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2560039
Goel NKumar APanda P(2014)Shared-port register file architecture for low-energy VLIW processorsACM Transactions on Architecture and Code Optimization10.1145/253339711:1(1-32)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1145/2533397
Xiao CCasseau EWang SLiu W(2014)Automatic custom instruction identification for application-specific instruction set processorsMicroprocessors & Microsystems10.1016/j.micpro.2014.09.00138:8(1012-1024)Online publication date: 1-Nov-2014
https://dl.acm.org/doi/10.1016/j.micpro.2014.09.001
Ma YChao WLiu T(2014)Enabling energy-proportional computing on instruction-level parallel processorsThe Journal of Supercomputing10.1007/s11227-014-1301-z71:2(391-447)Online publication date: 5-Oct-2014
https://doi.org/10.1007/s11227-014-1301-z
de Dinechin B(2014)Using the SSA-Form in a Code GeneratorCompiler Construction10.1007/978-3-642-54807-9_1(1-17)Online publication date: 2014
https://doi.org/10.1007/978-3-642-54807-9_1
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