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The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-Offs

Published: 01 January 1989 Publication History

Abstract

The Cydra 5 is a heterogeneous multiprocessor system that targets small work groups or departments of scientists and engineers. The two types of processors are functionally specialized for the different components of the work load found in a departmental setting. The Cydra 5 numeric processor, based on a directed-data-flow architecture, provides consistently high performance on a broader class of numerical computations. The interactive processors offload all nonnumeric work from the numeric processor, leaving it free to spend all its time on the numeric application. The I/O processors permit high-bandwidth I/O transitions with minimal involvement from the interactive or numeric processors. The system architecture and data-flow architecture are described. The numeric processor decisions and tradeoffs are examined, and the main memory system is discussed. Some reflections on the design issues are offered.

References

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Reviews

Peter C. Patton

The Cydra 5 departmental supercomputer was designed for small work groups or departments of scientists and engineers. It costs about the same as a high-end superminicomputer but it can achieve about one-third to one-half the performance of a supercomputer. It does this by using high-speed, air-cooled, emitter-coupled-logic technology in a product that includes many architectural innovations. The Cydra 5 is a heterogeneous multiprocessor system. The two types of processors are functionally specialized for the different components of the workload found in a departmental setting. The numeric processor, a proprietary device based on directed-dataflow architecture, is aided by a stride-insensitive high-bandwidth main memory system. Interactive processors offload all nonnumeric work from the numeric processor, leaving it free for numerical computation. The Cydra 5 grew out of eight years of research and development that dates back to work done at TRW Array Processors and at ESL (a subsidiary of TRW). The polycyclic architecture developed at TRW and ESL was a precursor of the directed-dataflow architecture developed at Cydrome starting in 1984. The common theme that linked both efforts was the desire to support a dataflow model of computation with as simple a hardware platform as possible. The driving force behind the development of the Cydra 5 was the desire to achieve increased performance over superminis on numerically intensive computations in such a way that the user would not have to discard the software, algorithms, training, or techniques acquired over the years. As a result, the user would be able to move up from the supermini to the minisuper in a transparent fashion. Transparency is important for a product such as the Cydra 5, which is aimed at the growth phase of the minisupercomputer market. Such a product must cater to a broader and less forgiving user group than the pioneers and early adopters who purchased first-generation minisupercomputers. The ideal sought by the design group was to match the “feel” of a conventional minicomputer, such as a VAX, with much higher performance. This paper provides an excellent study of the practical application of a dataflow architecture to a numerical computation environment. A number of Cydra 5 systems are in use at customer sites, and their performance has met the design team's expectations. On such industry-standard benchmarks as Linpack and the Livermore FORTRAN Kernels, the Cydra 5 delivers 15.4 and 5.8 Mflops, respectively. This is the highest performance of any minisupercomputer, including those whose peak performance is twice that of the Cydra, and about one-third the performance of a Cray X-MP, which has nine times the Cydra 5's peak performance. Across a spectrum of typical applications the Cydra 5 achieves between one-fourth and two-thirds of the performance of a Cray X-MP single processor, depending on the extent to which the application is vectorizable.

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Published In

cover image Computer
Computer  Volume 22, Issue 1
January 1989
87 pages
ISSN:0018-9162
Issue’s Table of Contents

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 January 1989

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