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A router architecture for real-time point-to-point networks

Published: 01 May 1996 Publication History

Abstract

Parallel machines have the potential to satisfy the large computational demands of emerging real-time applications. These applications require a predictable communication network, where time-constrained traffic requires bounds on latency or throughput while good average performance suffices for best-effort packets. This paper presents a router architecture that tailors low-level routing, switching, arbitration and flow-control policies to the conflicting demands of each traffic class. The router implements deadline-based scheduling, with packet switching and table-driven multicast routing, to bound end-to-end delay for time-constrained traffic, while allowing best-effort traffic to capitalize on the low-latency routing and switching schemes common in modern parallel machines. To limit the cost of servicing time-constrained traffic, the router shares packet buffers and link-scheduling logic between the multiple output ports. Verilog simulations demonstrate that the design meets the performance goals of both traffic classes in a single-chip solution.

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cover image ACM Conferences
ISCA '96: Proceedings of the 23rd annual international symposium on Computer architecture
May 1996
318 pages
ISBN:0897917863
DOI:10.1145/232973
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 24, Issue 2
    Special Issue: Proceedings of the 23rd annual international symposium on Computer architecture (ISCA '96)
    May 1996
    303 pages
    ISSN:0163-5964
    DOI:10.1145/232974
    Issue’s Table of Contents

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Published: 01 May 1996

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May 22 - 24, 1996
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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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  • (2005)Performance analysis of a QoS capable cluster interconnectPerformance Evaluation10.1016/j.peva.2004.10.00860:1-4(275-302)Online publication date: 1-May-2005
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