[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ Skip to main content
Springer Nature Link
Log in

The torus routing chip

  • Original Articles
  • Published:
Distributed Computing Aims and scope Submit manuscript

Abstract

The torus routing chip (TRC) is a selftimed chip that performs deadlock-freecut-through routing ink-aryn-cube multiprocessor interconnection networks using a new method of deadlock avoidance calledvirtual channels. A prototype TRC with byte wide self-timed communication channels achieved on first silicon a throughput of 64 Mbits/s in each dimension, about an order of magnitude better performance than the communication networks used by machines such as the Caltech Cosmic Cube or Intel iPSC. The latency of the cut-through routing of only 150 ns per routing step largely eliminates message locality considerations in the concurrent programs for such machines. The design and testing of the TRC as a self-timed chip was no more difficult than it would have been for a synchronous chip.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
£29.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (United Kingdom)

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Bryant R, Schuster M, Whiting D (1983) MOSSIM II: A Switch-Level Simulator for MOS LSI User's manual Caltech Tech Rep 5033: TR: 82 (January)

  2. Dally WJ, Seitz CL (1986) Deadlock-free message routing in multiprocessor interconnection networks. Dept Comput Sci, California Institute of Technology, Tech Rep 5206: TR:86

  3. Dally WJ: CNTK: An embedded language for circuit description. Dept Comput Sci, California Institute of Technology, Display File (in preparation)

  4. Fisher AL, Kung HT (1985) Synchronizing large VLSI Processor arrays. IEEE Trans Comp, C-34(8) 734–740

    Google Scholar 

  5. Gunther KD (1981) Prevention of deadlocks in packetswitched data transport systems. IEEE Trans Commun COM-29, (4) 512–524

    Google Scholar 

  6. Intel iPSC User's Guide (1985) Intel Document No. 175455-001 (August)

  7. Kermani, P, Kleinrock L (1979) Virtual, cut-through: a new computer communication switching technique. Comput Networks 3:267–286

    Google Scholar 

  8. Kleinrock L (1976) Queuing systems; vol 2. Wiley, New York, pp 438–440

    Google Scholar 

  9. Lang CR (1982) The extension of object-oriented languages to a homogeneous concurrent architecture. Dept. of Computer Science, California Institute of Technology, Technical Report, 5014: TR:82 118–124

  10. Ousterhout, JK et al. (1985) The magic VLSI layout system. IEEE Design and Test of Computers, 2(1), 19–30

    Google Scholar 

  11. Seitz, CL (1980) System Timing. In: Mead CA, Conway LA, Introduction to VLSI Systems, Addison Wesley, London Amsterdam Paris

    Google Scholar 

  12. Seitz CL (1984) Concurrent VLSI Architectures. IEEE Trans Comput, C-33(12), 1247–1265

    Google Scholar 

  13. Seitz CL (1985) The cosmic cube CACM, 28(1), 22–33

    Google Scholar 

  14. Seitz CL et al. (1985) The Hypercube Commun Chip. Dept. of Computer Science, California Institute of Technology, Display Fiel 5182: DF:85

  15. Steele CS (1985) Placement of communicating processes on multiprocessor networks. Dept Comput Sci, California Institute of Technology, Tech Rep 5184:TR:85.

    Google Scholar 

  16. Tanenbaum AS (1981) Comput networks. Prentice Hall, Englwood Cliffs, NJ, pp 15–21

    Google Scholar 

  17. Trotter D (1985) Miss MOSIS, Scalable CMOS Rules, Version 1.2

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science, California Institute of Technology, Pasadena, CA, USA

    William J. Dally & Charles L. Seitz

Authors
  1. William J. Dally
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Charles L. Seitz
    View author publications

    You can also search for this author in PubMed Google Scholar

Additional information

Bill Dally received his B. S. degree in Electrical Engineering from the Virginia Polytechnic Institute in 1980 and his M.S. degree in Electrical Engineering from Stanford University in 1981. From 1980 to 1982 he worked at Bell Telephone Laboratories, where he contributed to the design of the BELLMAC-32 microprocessor. From 1982 to 1983 he worked as a consultant in the area of digital systems design. Since 1983 he has been a graduate student in Computer Science at Caltech, and is expected to complete his Ph.D. studies in the spring 1986. His current research interests include computer architecture, computer aided design, VLSI, design, and concurrent systems.

Chuck Seitz earned B.S., M.S., and Ph.D. degrees from M.I.T. Before joining the Computer Science faculty at Caltech in 1977, he worked as a member of the technical staff of the Evans & Sutherland Computer Corporation from 1969 to 1971, as an Assistant Professor of Computer Science at the University of Utah from 1970 to 1972, and as a consultant to Burroughs Corporation from 1971 to 1978. He is currently a Professor of Computer Science at Caltech, where his research and teaching activities are in the areas of VLSI architecture and design, concurrent computation, and self-timed systems.

The research described in this paper was sponsored in part by the Defense Advanced Research Projects Agency, ARPA Order number 3771, and monitored by the Office, of Naval Research under contract number N 00014-79-C-0597, in part by Intel Corporation, and in part by an AT & T Ph.D. fellowship

Rights and permissions

Reprints and permissions

About this article

Cite this article

Dally, W.J., Seitz, C.L. The torus routing chip. Distrib Comput 1, 187–196 (1986). https://doi.org/10.1007/BF01660031

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF01660031

Key words

Search

Navigation