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A methodology for fast FPGA floorplanning

Authors:

John M. Emmert,

Dinesh BhatiaAuthors Info & Claims

FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

Pages 47 - 56

https://doi.org/10.1145/296399.296427

Published: 01 February 1999 Publication History

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References

[1]

Altera Inc. http://www, altera, com.

Google Scholar

[2]

V. Betz and J. Rose. VPR: A New Packing, Placement, and Routing Tool for FPGA Research. In Lecture Notes in Computer Science, volume 1304, pages 213-222. Springer-Verlag, 1997.

Digital Library

Google Scholar

[3]

T J. Callahan, P. Chong, A. DeHon, and J. Wawrzynek. Fast Module Mapping and Placement for Datapaths in FP- GAs. In A CM/SIGDA International Symposium on Field- Programmable Gate Arrays, pages 123-132, Feburary 1998.

Digital Library

Google Scholar

[4]

J.M. Emmert and D. K. Bhatia. ReconfiguringFPGA Mapped Designs with Applications to Fault Tolerance and Reconfigurable Computing. In Lecture Notes in Computer Science, volume 1304, pages 141-150. Springer-Verlag, 1997.

Digital Library

Google Scholar

[5]

J. M. Emmert and D. K. Bhatia. University of Cincinnati Technical Report Number: TR219/09/98/ECECS, 1998.

Google Scholar

[6]

F. Glover and M. Laguna. Tabu Search. Kluwer Academic Publishers, 1997.

Digital Library

Google Scholar

[7]

D. E. Goldberg. Genetic Algorithms in Search, Optimization, and Machine Learning. Addison-Wesley Publishing Company, 1989.

Digital Library

Google Scholar

[8]

S. Kirkpatrick, D. D. Gelatt, and M. P. Vecchi. Optimization by Simulated Annealing. Science, 220:671-680, May 1983.

Google Scholar

[9]

H. Kmpnova, C. Rabedaoro, and G. Saucier. Synthesis and Floorplanning for Large Hierarchical FPGAs. In A CM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 105-111, Feburary 1997.

Digital Library

Google Scholar

[10]

F. T Leighton and P. W. Shor. Tight Bounds for Minimax Grid Matching with Applications to Average Case Analysis of Algorithms. in Proceedings of the Symposium on Theory of Computing, pages 91-103, May 1986.

Digital Library

Google Scholar

[11]

A. Lim. Performance Driven Placement Using Tabu Search. Informatica, 7(1 ), 1996.

Google Scholar

[12]

A. Lim, Y. M. Chee, and C. T. Wu. Performance Driven Placement with Global Routing for Macro Cells. In Proceedings of Second Great Lakes Symposium on VLSI, pages 35-41, 1991.

Crossref

Google Scholar

[13]

A. Mathur, K. C. Chen, and C. L. Liu. Re-engineering of Timing Constrained Placements for Regular Architectures. In IEEFIA CM International Conference on Computer Aided Design, pages 485-490, November 1995.

Digital Library

Google Scholar

[14]

S.M. Sait and H. Youssef. VLSI Physical Design Automation. IEEE Press, 1995.

Digital Library

Google Scholar

[15]

J. Shi and D. Bhatia. Performance Driven Floorplanning for FPGA Based Designs. In A CM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 112-118, Feburary 1997.

Digital Library

Google Scholar

[16]

L. Song and A. Vannelli. A VLSI Placement Method Using Tabu Search. In Microelectronics Journal, number 3, pages 167-172, May 1992.

Google Scholar

[17]

N. Togawa, M. Yanagisawa, and T. Ohtsuki. Maple-opt: A Performance-Oriented Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGA's. IEEE Transactions on Compter-Aided Design of lntegrated Circuits and Systems, 17:803-823, September 1998.

Digital Library

Google Scholar

[18]

T. Yamanouchi, K. Tamakashi, and T. Kambe. Hybrid Floorplanning Based on Partial Clustering and Module Restructuring. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 478-483, 1996.

Digital Library

Google Scholar

[19]

Xilinx Inc. http://www, xilinx, com.

Google Scholar

Cited By

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Khvatov VGavrilov S(2023)Formation of IP-Core Libraries in the User IC Design Flow for FPGAs and RSoCsRussian Microelectronics10.1134/S106373972207006X51:7(567-572)Online publication date: 9-Jan-2023
https://doi.org/10.1134/S106373972207006X
Khvatov VZheleznikov D(2021)Development of an IP-cores Libraries as Part of the Design Flow of Integrated Circuits on FPGA2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)10.1109/ElConRus51938.2021.9396219(2686-2691)Online publication date: 26-Jan-2021
https://doi.org/10.1109/ElConRus51938.2021.9396219
Gharibian FShannon LJamieson P(2014)Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data2014 24th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2014.6927479(1-6)Online publication date: Sep-2014
https://doi.org/10.1109/FPL.2014.6927479
Show More Cited By

Index Terms

A methodology for fast FPGA floorplanning
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Hardware

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Published In

FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

February 1999

257 pages

ISBN:1581130880

DOI:10.1145/296399

Chairmen:
Sinan Kaptanoglu
Actel Corporation
,
Steve Trimberger
Xilinx

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 February 1999

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FPGA99

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SIGDA

FPGA99: ACM/SIGDA Symposium on Field Programmable Gate Arrays

February 21 - 23, 1999

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

View all

Khvatov VGavrilov S(2023)Formation of IP-Core Libraries in the User IC Design Flow for FPGAs and RSoCsRussian Microelectronics10.1134/S106373972207006X51:7(567-572)Online publication date: 9-Jan-2023
Khvatov VZheleznikov D(2021)Development of an IP-cores Libraries as Part of the Design Flow of Integrated Circuits on FPGA2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)10.1109/ElConRus51938.2021.9396219(2686-2691)Online publication date: 26-Jan-2021
Gharibian FShannon LJamieson P(2014)Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data2014 24th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2014.6927479(1-6)Online publication date: Sep-2014
Gharibian FShannon LJamieson PChung K(2013)Analyzing System-Level Information’s Correlation to FPGA PlacementACM Transactions on Reconfigurable Technology and Systems10.1145/25019856:3(1-21)Online publication date: 1-Oct-2013
Jamieson PGharibian FShannon L(2013)Supergenes in a genetic algorithm for heterogeneous FPGA placement2013 IEEE Congress on Evolutionary Computation10.1109/CEC.2013.6557578(253-260)Online publication date: Jun-2013
Wood AKnight AYlvisaker BHauck S(2012)Multi-kernel floorplanning for enhanced CGRAS22nd International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2012.6339255(157-164)Online publication date: Aug-2012
Kahoul ASmith AConstantinides GCheung P(2010)Efficient Heterogeneous Architecture Floorplan Optimization using Analytical MethodsACM Transactions on Reconfigurable Technology and Systems10.1145/1857927.18579304:1(1-23)Online publication date: 1-Dec-2010
Gharibian FShannon LJamieson P(2010)Finding System-Level Information and Analyzing Its Correlation to FPGA PlacementProceedings of the 2010 International Conference on Field Programmable Logic and Applications10.1109/FPL.2010.107(544-549)Online publication date: 31-Aug-2010
Hauck SDeHon A(2007)Reconfigurable ComputingundefinedOnline publication date: 2-Nov-2007
Feng YMehta D(2006)Heterogeneous Floorplanning for FPGAsProceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design10.1109/VLSID.2006.96(257-262)Online publication date: 3-Jan-2006
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MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs

Hybrid floorplanning based on partial clustering and module restructuring

Fast floorplanning by look-ahead enabled recursive bipartitioning