Abstract
Complex functional blocks or intellectual property (IP) cores are developed and used to speed up the user IC design flow and improve their final characteristics. There are two IP-cores types—soft IP-cores and hard IP-cores. A hard IP core has a fixed on-chip layout and pre-routed interconnects, while a soft IP core consists of logic gates and requires placement and routing. For an automated flow for designing ICs based on FPGAs and reconfigurable systems on a chip (RSoC) it is necessary to develop core libraries that allow them to be identified at each stage of the design flow. The paper shows various types and formats of libraries of soft and hard IP-cores used in the design flow for ICs based on FPGAs and Russian-made RSoCs. Methods for designing libraries of necessary CAD systems at the stages of logical synthesis, automatic technological mapping and layout synthesis are described. The characteristic features of soft and hard IP-cores libraries, as well as methods for their formation, are considered taking into account the architecture of FPGAs and RSoCs. The proposed design methods make it possible to develop libraries that are necessary for the automated implementation of all types of IP-cores, taking into account the advantages of the architecture of basic FPGAs and RSoCs.
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This work was supported by the Russian Foundation for Basic Research (project no. 20-37-90047).
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Khvatov, V.M., Gavrilov, S.V. Formation of IP-Core Libraries in the User IC Design Flow for FPGAs and RSoCs. Russ Microelectron 51, 567–572 (2022). https://doi.org/10.1134/S106373972207006X
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DOI: https://doi.org/10.1134/S106373972207006X