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Estimation of maximum power supply noise for deep sub-micron designs

Authors:

Yi-Min Jiang,

Kwang-Ting Cheng,

An-Chang DengAuthors Info & Claims

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

Pages 233 - 238

https://doi.org/10.1145/280756.280915

Published: 10 August 1998 Publication History

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Abstract

We propose a new technique for generating a small set of patterns to estimate the maximum power supply noise of deep sub-micron designs. We first build the charge/discharge current and output voltage waveform libraries for each cell, taking power and ground pin characteristics, the power net RC and other input characteristics as parameters. Based on the cells' current and voltage libraries, the power supply noise of a 2-vector sequence can be estimated efficiently by a cell-level waveform simulator. We then apply the Genetic Algorithm based on the efficient waveform simulator to generate a small set of patterns producing high power supply noise. Finally, the results are validated by simulating the obtained patterns using a transistor level simulator. Our experimental results show that the patterns generated by our approach produce a tight lower bound on the maximum power supply noise.

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Cited By

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Ding WHsieh HHan CLi JWen X(2016)Test Pattern Modification for Average IR-Drop ReductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239129124:1(38-49)Online publication date: Jan-2016
https://doi.org/10.1109/TVLSI.2015.2391291
Tsai MDing WHsieh HLi J(2014)Transient IR-Drop Analysis for At-Speed Testing Using Representative Random WalkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.228061622:9(1980-1989)Online publication date: Sep-2014
https://doi.org/10.1109/TVLSI.2013.2280616
Cheng C(2014)The efficient circuit delay evaluation/diagnosis methodology under voltage drop2014 International Symposium on Next-Generation Electronics (ISNE)10.1109/ISNE.2014.6839363(1-4)Online publication date: May-2014
https://doi.org/10.1109/ISNE.2014.6839363
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Estimation of maximum power supply noise for deep sub-micron designs

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Published In

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

August 1998

318 pages

ISBN:1581130597

DOI:10.1145/280756

Chairmen:
Anantha Chandrakasan
MIT
,
Sayfe Kiaei
Motorola

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 August 1998

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ISLPED98: International Symposium on Low Power Electronics and Design

August 10 - 12, 1998

California, Monterey, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Ding WHsieh HHan CLi JWen X(2016)Test Pattern Modification for Average IR-Drop ReductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239129124:1(38-49)Online publication date: Jan-2016
https://doi.org/10.1109/TVLSI.2015.2391291
Tsai MDing WHsieh HLi J(2014)Transient IR-Drop Analysis for At-Speed Testing Using Representative Random WalkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.228061622:9(1980-1989)Online publication date: Sep-2014
https://doi.org/10.1109/TVLSI.2013.2280616
Cheng C(2014)The efficient circuit delay evaluation/diagnosis methodology under voltage drop2014 International Symposium on Next-Generation Electronics (ISNE)10.1109/ISNE.2014.6839363(1-4)Online publication date: May-2014
https://doi.org/10.1109/ISNE.2014.6839363
Alpaslan EKruseman BMajhi AHeuvalman WDworak J(2012)NIM-XIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.217904031:5(809-813)Online publication date: 1-May-2012
https://dl.acm.org/doi/10.1109/TCAD.2011.2179040
Varma P(2012)Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network ValidationProceedings of the 2012 IEEE 21st Asian Test Symposium10.1109/ATS.2012.68(233-238)Online publication date: 19-Nov-2012
https://dl.acm.org/doi/10.1109/ATS.2012.68
Firouzi FKiamehr STahoori MPhillips JHu AGraeb H(2011)Modeling and estimation of power supply noise using linear programmingProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132450(537-542)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132450
Padmawar MRoy SChakraborty K(2011)Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770727(1-7)Online publication date: Mar-2011
https://doi.org/10.1109/ISQED.2011.5770727
Firouzi FKiamehr STahoori M(2011)Modeling and estimation of power supply noise using linear programmingProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105382(537-542)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.1109/ICCAD.2011.6105382
Wu TSambamurthy SAbraham J(2010)Estimation of maximum application-level power supply noise23rd IEEE International SOC Conference10.1109/SOCC.2010.5784738(213-218)Online publication date: Sep-2010
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Phong YCheng CGuo J(2010)Efficient IR drop analysis and alleviation methodologies using dual threshold voltages with gate resizing techniquesThe 2010 International Conference on Green Circuits and Systems10.1109/ICGCS.2010.5543081(129-132)Online publication date: Jun-2010
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