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Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability

Published: 29 September 2015 Publication History

Abstract

Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling and increasing temperatures due to growing power density are threatening lifetime reliability. Negative bias temperature instability (NBTI) has been known for decades, but its impact has been insignificant compared to other factors. Aggressive scaling, however, makes NBTI the most serious threat to chip lifetime reliability in today's and future process technologies. The delay of microprocessors gradually increases as time goes by, due to stress and recovery phases. The delay eventually becomes higher than the value required to meet design constraints, which results in failed systems. In this article, the mechanism of NBTI and its effects on lifetime reliability are presented, then various techniques to mitigate NBTI degradation on microprocessors are introduced. The mitigation can be addressed at either the circuit level or architectural level. Circuit-level techniques include design-time techniques such as transistor sizing and NBTI-aware synthesis. Forward body biasing, and adaptive voltage scaling are adaptive techniques that can mitigate NBTI degradation at the circuit level by controlling the threshold voltage or supply voltage to hide the lengthened delay caused by NBTI degradation. Reliability has been regarded as something to be addressed by chip manufacturers. However, there are recent attempts to bring lifetime reliability problems to the architectural level. Architectural techniques can reduce the cost added by circuit-level techniques, which are based on the worst-case degradation estimation. Traditional low-power and thermal management techniques can be successfully extended to deal with reliability problems since aging is dependent on power consumption and temperature. Self-repair is another option to enhance the lifetime of microprocessors using either core-level or lower-level redundancy. With a growing thermal crisis and constant scaling, lifetime reliability requires more intensive research in conjunction with other design issues.

References

[1]
W. Abadeer and W. Ellis. 2003. Behavior of NBTI under AC dynamic circuit conditions. In Proceedings of the IEEE International Reliability Physics Symposium. 17--22.
[2]
S. Aota, S. Fujii, Z. W. Jin, Y. Ito, K. Utsumi, E. Morifuji, S. Yamada, F. Matsuoka, and T. Noguchi. 2005. A new method for precise evaluation of dynamic recovery of negative bias temperature instability. In Proceedings of the IEEE International Conference on Microelectronic Test Structures. 197--199.
[3]
N. Ayala, J. Martin-Martinez, E. Amat, M. B. Gonzalez, P. Verheyen, R. Rodriguez, M. Nafria, X. Aymerich, and E. Simoen. 2011. NBTI related time-dependent variability of mobility and threshold voltage in pMOSFETs and their impact on circuit performance. Microelectronic Engineering 88, 7, 1384--1387.
[4]
M. Basoglu, M. Orshansky, and M. Erez. 2010. NBTI-aware DVFS: A new approach to saving energy and increasing processor lifetime. In Proceedings of the ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED). 253--258.
[5]
D. R. Bild, G. E. Bok, and R. P. Dick. 2009. Minimization of NBTI performance degradation using internal node control. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’09). 148--153.
[6]
S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De. 2003. Parameter variations and impact on circuits and microarchitecture. In Proceedings of the ACM/IEEE Design Automation Conference. 338--342.
[7]
K. A. Bowman, S. G. Duvall, and J. D. Meindl. 2002. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE Journal of Solid-State Circuits 37, 2, 183--190.
[8]
A. Calimera, E. Macii, and M. Poncino. 2009. NBTI-aware power gating for concurrent leakage and aging optimization. In Proceedings of the International Symposium on Low Power Electronics and Design. 127--132.
[9]
Yunus A. Cengel. 1997. Introduction to thermodynamics and heat. McGraw Hill Higher Education, Chicago, IL.
[10]
T. Chan, J. Sartori, P. Gupta, and R. Kumar. 2011. On the efficacy of NBTI mitigation techniques. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’11). 1--6.
[11]
T.-B. Chan, W.-T. J. Chan, and A. B. Kahng. 2013. Impact of adaptive voltage scaling on aging-aware signoff. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’13). 1683--1688.
[12]
A. Chaudhary and S. Mahapatra. 2013. A physical and SPICE mobility degradation analysis for NBTI. IEEE Transactions on Electronic Devices 60, 7, 2096--2103.
[13]
G. Chen, K. Y. Chuah, M.-F. Li, D. S. H. Chan, C. H. Ang, J. Z. Zheng, Y. Jin, and Kwong, D. L. Kwong. 2002. Dynamic NBTI of PMOS transistors and its impact on device lifetime. IEEE Electron Device Letter 734--736.
[14]
X. Chen, Y. Wang, Y. Cao, Y. Ma, and H. Yang. 2012. Variation-aware supply voltage assignment for simultaneous power and aging optimization. IEEE Transactions on Very Large Scale Integration Systems 20, 11, 2143--2147.
[15]
B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow. 1967. Characteristics of the surface-state charge (Qss) of thermally oxidized silicon. Journal of the Electrochemical Society 114, 3, 266--274.
[16]
M. Denais, C. Parthasarathy, G. Ribes, Y. Rey-Tauriac, N. Revil, A. Bravaix, V. Huard, and F. Perrier. 2004. On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET's. In Proceedings of the IEEE International Electron Devices Meeting. 109--112.
[17]
M. Ebrahimi, F. Oboril, S. Kiamehr, and M. B. Tahoori. 2013. Aging-aware logic synthesis. In Proceedings of the International Conference on Computer-Aided Design (ICCAD).
[18]
S. Feng, S. Gupta, A. Ansari, and S. Mahlke. 2010. Maestro: Orchestrating lifetime reliability in chip multiprocessors. In Proceedings of the International Conference on High Performance Embedded Architectures and Compilers. 186--200.
[19]
R. Ferńandez, B. Kaczer, A. Nackaerts, S. Demuynck, R. Rodriguez, M. Nafria, and G. Groeseneken. 2006. AC NBTI studied in the 1 Hz--2 GHz range on dedicated on-chip circuits. In Proceedings of the IEEE International Electron Devices Meeting. 337--340.
[20]
D. Frohman-Bentchkowsky. 1971. A fully decoded 2048-bit electrically programmable FAMOS read-only memory. IEEE Journal of Solid-State Circuits 6, 5, 301--306.
[21]
X. Fu, T. Li, and J. Fortes. 2008. NBTI tolerant microarchitecture design in the presence of process variation. In Proceedings of 41st IEEE /ACM International Symposium on Microarchitecture. 399--410.
[22]
Seyab S. Hamdioui. 2010. NBTI modeling in the framework of temperature variation. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’10). 283--286.
[23]
J. Henkel, Bauer, L. N. Dutt, P. Gupta, and S. Nassif. 2013. Reliable on-chip systems in the nano-era: Lessons learnt and future trends. In Proceedings of the ACM/IEEE Design Automation Conference (DAC). 1--10.
[24]
J. Hicks, E. Bergstrom, M. Hattendorf, J. Jopling, J. Maiz, S. Pae, C. Prasad, and J. Wiedemer. 2008. 45 nm Transistor Reliability. Intel Technology Journal 12, 2, 131--144.
[25]
L. Huang and Q. Xu. 2010a. Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’10). 1584--1589.
[26]
L. Huang and Q. Xu. 2010b. Characterizing the lifetime reliability of manycore processors with core-level redundancy. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). 680--685.
[27]
L. Huang, F. Yuan, and Q. Xu. 2011. On task allocation and scheduling for lifetime extension of platform-based MPSoC designs. IEEE Transactions on Parallel and Distributed Systems 22, 12, 2088--2099.
[28]
V. Huard and M. Denais. 2004. Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in PMOS transistors. In Proceedings of the International Reliability Physics Symposium. 40--45.
[29]
V. Huard, M. Denais, and C. Parthasarathy. 2006. NBTI degradation: From physical mechanisms to modeling. Microelectronics Reliability 46, 1, 1--23.
[30]
V. Huard, C. Parthasarathy, N. Rallet, C. Guerin, M. Mammase, D. Barge, and C. Ouvrard. 2007. New characterization and modeling approach for NBTI degradation from transistor to product level. In Proceedings of the IEEE International Electron Devices Meeting (IEDM). 797--800.
[31]
T. Jin and S. Wang. 2012. Aging-aware instruction cache design by duty cycle balancing. In Proceedings of the Computer Society Annual Symposium on VLSI. 195--200.
[32]
K. Kang, H. Kufluoglu, M. A. Alain, and K. Roy. 2006. Efficient transistor-level sizing technique under temporal performance degradation due to NBTI. In Proceedings of the International Conference on Computer Design (ICCD’06).
[33]
K. Kang, S. Gangwal, S. Park, and K. Roy. 2008. NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? In Proceedings of the Asia and South Pacific Design Automation Conference. 726--731.
[34]
G. Karakonstantis, C. Augustine, and K. Roy. 2010. A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique. In Proceedings of the IEEE 16th International On-Line Testing Symposium (IOLTS). 3--8.
[35]
U. R. Karpuzcu, B. Greskamp, and J. Torrellas. 2009. The BubbleWrap many-core: Popping cores for sequential acceleration. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO’09). 447--458.
[36]
J. Keane, T.-H. Kim, and C. H. Kim. 2010. An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. IEEE Transactions on Very Large Scale Integration Systems 18, 6, 947--956.
[37]
J. Keane, D. Persaud, and. C. H. Kim. 2009. An all-in-one silicon Odometer for separately monitoring HCI, BTI, and TDDB. In Proceedings of the IEEE Symposium on VLSI Circuits. 108--109.
[38]
M. B. Ketchen, M. Bhushan, and R. Bolam. 2007. Ring oscillator based test structure for NBTI analysis. In Proceedings of the IEEE International Conference on Microelectronic Test Structures. 42--47.
[39]
S. Khan, N. Z. Haron, S. Hamdioui, and F. Catthoor. 2011. NBTI monitoring and design for reliability in nanoscale circuits. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). 68--76.
[40]
T.-H. Kim, R. Persaud, and C. H. Kim. 2008. Silicon odometer: An on-chip reliability monitor for measuring frequency degradation of digital circuits. IEEE Journal of Solid-State Circuits 43, 4, 874--880.
[41]
P. Ko, J. Huang, Z. Liu, and C. Hu. 1993. BSIM3 for analog and digital circuit simulation. In Proceedings of the IEEE Symposium on VLSI Technology CAD. 400--429.
[42]
S. K. Krishnappa and H. Mahmoodi. 2011. Comparative BTI reliability analysis of SRAM cell designs in nano-scale CMOS technology. In Proceedings of the IEEE International Symposium on Quality Electronic Design. 1--6.
[43]
S. Kumar, K. H. Kim, and S. S. Sapatnekar. 2006. Impact of NBTI on SRAM read stability and design for reliability. In Proceedings of the IEEE International Symposium on Quality Electronic Design. 210--218.
[44]
S. V. Kumar, C. H. Kim, and S. S. Sapatnekar. 2007. NBTI-aware synthesis of digital circuits. In Proceedings of the ACM/IEEE Design Automation Conference (DAC). 370--375.
[45]
S. V. Kumar, C. H. Kim, and S. S. Sapatnekar. 2011. Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, 4, 603--614.
[46]
G. La Rosa, F. Guarin, S. Rauch, A. Acovic, J. Lukaitis, and E. Crabbe. 1997. NBTI-channel hot carrier effects in PMOSFETs in advanced CMOS technologies. In Proceedings of the IEEE International Reliability Physics Symposium. 282--286.
[47]
L. Lai, V. Chandra, R. Aitken, and P. Gupta. 2014. BTI-Gater: An aging-resilient clock gating methodology. IEEE Journal on Emerging and Selected Topics in Circuits and System 4, 2, 180--189.
[48]
Y. Lee and T. Kim. 2011. A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs. In Proceedings of the Asia and South Pacific Design Automation Conference. 603--608.
[49]
L. Li, Y. Zhang, and J. Yang. 2011. Proactive recovery for BTI in high-k SRAM cells. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’11). 1--6.
[50]
Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko, and Y. C. Cheng. 1993. Threshold voltage model for deep submicrometer MOSFETs. IEEE Transactions on Electron Devices 40, 1, 86--95.
[51]
Y. Lu, L. Shang, H. Zhou, F. Yang, and X. Zeng. 2009. Statistical reliability analysis under process variation and aging effects. In Proceedings of the ACM/IEEE Design Automation Conference (DAC). 514--519.
[52]
H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki. 2005. Challenge: Variability characterization and modeling for 65-nm to 90-nm processes. In Proceedings of the IEEE Custom Integrated Circuits Conference (CICC). 593--599.
[53]
E. Mintarno, J. Sckaf, R. Zheng, J. B. Velamala, Y. Cao, S. Boyd, R. W. Dutton, and S. Mitra. 2011. Self-tuning for maximized lifetime energy-efficiency in the presence of circuit aging. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, 5, 760--773.
[54]
H. Mostafa, M. Anis, and M. Elmasry. 2011. Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells. IEEE Transactions on Circuits and Systems I 58, 12, 2859--2871.
[55]
H. Mostafa, M. Anis, and M. Elmasry. 2012. NBTI and process variations compensation circuits using adaptive body bias. IEEE Transactions on Semiconductor Manufacturing 25, 3, 460--467.
[56]
S. Narendra, A. Keshavarzi, B. A. Bloechel, S. Borkar, and V. De. 2003. Forward body bias for microprocessors in 130-nm technology generation and beyond. IEEE Journal of Solid State Circuits 38, 5, 696--701.
[57]
A. Neugroschel, C. T. Sah, K. M. Han, M. S. Carroll, T. Nishida, J. T. Kavalieros, and Y. Lu. 1995. Direct-current measurement of oxide and interface traps on oxidized silicon. IEEE Transactions on Electron Devices 42, 9, 1657--1662.
[58]
F. Oboril and M. B. Tahoori. 2012a. Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation. In Proceedings of the IEEE European Test Symposium (ETS). 1--6.
[59]
F. Oboril and M. B. Tahoori. 2012b. ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level reducing. In Proceedings of the IEEE International Conference on Dependable Systems and Networks (DSN).
[60]
F. Oboril, F. Firouzi, S. Kiamehr, and M. B. Tahoori. 2013. Negative bias temperature instability-aware instruction scheduling: A cross-layer approach. Journal of Low Power Electronics, 9, 4, 389--402.
[61]
S. Ogawa and N. Shiono. 1995. Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface. Physical Review B 51, 7, 4218--4230.
[62]
S. Pae, M. Agostinelli, M. Brazier, G. Chau, G. Dewey, Y. Ghani, M. Hattendorf, J. Hicks, J. Kavalieros, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, and J. Wiedemer. 2008. BTI reliability of 45 nm high-k + metal-gate process technology. IEEE International Reliability Physics Symposium 352--357.
[63]
B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy. 2005. Impact of NBTI on the temporal performance degradation of digital circuits. IEEE Electron Device Letter 560--562.
[64]
B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy. 2006. Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’06).
[65]
A. Pushkarna and H. Mahmoodi. 2010. Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in Nano-Scale CMOS. In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI).
[66]
Z. Qi and M. R. Stan. 2008. NBTI resilient circuits using adaptive body biasing. In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI). 285--290.
[67]
S. Rangan, N. Mielke, and E. C. C. Yeh. 2003. Universal recovery behavior of negative bias temperature instability. In Proceedings of the IEEE International Electron Devices Meeting. 341--344.
[68]
B. F. Romanescu and D. J. Sorin. 2008. Core cannibalization architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT). 1--10.
[69]
S. Roy and D. Z. Pan. 2014. Reliability aware gate sizing combating NBTI and oxide breakdown. In Proceedings of the International Conference on VLSI Design and International Conference on Embedded Systems. 38--43.
[70]
N. Sa, J. F. Kand, H. Yang, X. Y. Liu, Y. D. He, R. Q. Han, C. Ren, H. Y. Yu, D. S. H. Chan, and D. L. Kwong. 2002. Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps. IEEE Electron Device Letters 26, 9, 610--612.
[71]
T. Sakurai and A. R. Newton. 1990. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE Journal of Solid-State Circuits 25, 2, 584--594.
[72]
C. Shen, C. E. Li, M.-F. Foo, T. Yang, D. M. Huang, A. Yap, G. S. Samudra, and Y.-C. Yeo. 2006. Characterization and physical origin of fast Vth transient in NBTI of pMOSFETs with SiON dielectrics. In Proceedings of the IEEE International Electron Devices Meeting. 1--4.
[73]
T. Siddiqua and S. Gurumurthi. 2009. NBTI-aware dynamic instruction scheduling. In Proceedings of the IEEE Workshop on Silicon Errors in Logic--System Effects.
[74]
T. Siddiqua and S. Gurumurthi. 2010. A multi-level approach to reduce the impact of NBTI on processor functional units. In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI). 67--72.
[75]
T. Siddiqua, S. Gurumurthi, and M. R. Stan. 2011. Modeling and analyzing NBTI in the presence of process variation. In Proceedings of the Quality of Electronic Design (ISQED). 1--8.
[76]
P. Singh, E. Karl, D. Blaauw, and D. Sylvester. 2012. Compact degradation sensors for monitoring NBTI and oxide degradation. IEEE Transactions on Very Large Scale Integration Systems 20, 9, 1645--1655.
[77]
J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. 2004. The case for lifetime reliability-aware micorprocessors. In Proceedings of the International Symposium on Computer Architecture (ISCA’04).
[78]
J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. 2005a. Lifetime reliability: Toward an architectural solution. IEEE Micro 25, 3, 70--80.
[79]
J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. 2005b. Exploiting structural duplication for lifetime reliability enhancement. In Proceedings of the International Symposium on Computer Architecture (ISCA’05).
[80]
N. Strikos. 2013. Enhancing Lifetime Reliability Of Chip Multiprocessors Through 3D Resource Sharing. Master's thesis. University of California, San Diego.
[81]
J. Sun, A. Kodi, A. Louri, and J. M. Wang. 2009. NBTI aware workload balancing in multi-core systems. In Proceedings of the Quality of Electronic Design (ISQED). 833--838.
[82]
A. Tiwari and J. Torrellas. 2008. Facelift: Hiding and slowing down aging in multicores. In Proceedings of the International Symposium on Microarchitecture (MICRO). 129--140.
[83]
K. Uwasawa, T. Yamamoto, and T. Mogami. 1995. A new degradation mode of scaled p+ polysilicon gate pMOSFETs induced by bias temperature (BT) instability. In Proceedings of the IEEE International Electron Devices Meeting. 871--874.
[84]
R. Vattikonda, W. Wang, and Y. Cao. 2006. Modeling and minimization of PMOS NBTI effect for robust nanometer design. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’06). 1047--1052.
[85]
I. Wagner and V. Bertacco. 2008. Reversi: Post-silicon validation system for modern micro-processors. In Proceedings of the International Conference on Computer Design (ICCD’08).
[86]
W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, and Y. Cao. 2007a. The impact of NBTI on the performance of combinational and sequential circuits. In Proceedings of the ACM/IEEE Design Automation Conference. 364--369.
[87]
Y. Wang, H. Luo, K. He, R. Luo, H. Yang, and Y. Xie. 2007b. Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. In Proceedings of the Design, Automation and Test in Europe Conference (DATE’07). 546--551.
[88]
Y. Wang, X. Chen, W. Wang, V. Balakrishnan, Y. Cao, Y. Xie, and H. Yang. 2009. On the efficacy of input vector control to mitigate NBTI effects and leakage power. In Proceedings of the International Symposium on Quality of Electronic Design. 19--26.
[89]
Y. Wang, S. Cotofana, and F. Liang. 2011. A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET. In Proceedings of the International Symposium on Nanoscale Architectures (NANOARCH). 175--180.
[90]
M. White. 2008. Microelectronics reliability: physics-of-failure based modeling and lifetime evaluation. Technical Report. Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA.
[91]
H. Yang, W. Hwang, and C.-T. Chuang. 2011. Impacts of NBTI/PBTI and contact resistance on power-gated SRAM with high-k metal-gate devices. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, 7, 1192--1204.
[92]
X. Yang and S. Saluja. 2007. Combating NBTI degradation via gate sizing. In Proceedings of the Quality of Electronic Design (ISQED). 47--52.
[93]
S. Zafar, B. H. Lee, J. Stathis, and A. Callegari. 2004. A model for negative bias temperature instability (NBTI) in oxide and high k pFETs. In Proceedings of the Symposium on VLSI Technology. 208--209.
[94]
S. Zafar, Y. H. Kim, V. Narayanan, C. Cabral, V. Paruchuri, B. Doris, J. Stahis, A. Callegari, and M. Chudzik. 2006. A comparative study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates. In Proceedings of the Symposium on VLSI Technology. 23--25.
[95]
L. Zhang and R. P. Dick. 2009. Scheduled voltage scaling for increasing lifetime in the presence of NBTI. In Proceedings of the Asia and South Pacific Design Automation Conference. 492--497.
[96]
K. Zhao, J. H. Stathis, B. P. Linder, E. Cartier, and A. Kerber. 2011. PBTI under dynamic stress: From a single defect point of view. IEEE International Reliability Physics Symposium 4A.3.1--4A.3.9.

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cover image ACM Computing Surveys
ACM Computing Surveys  Volume 48, Issue 1
September 2015
592 pages
ISSN:0360-0300
EISSN:1557-7341
DOI:10.1145/2808687
  • Editor:
  • Sartaj Sahni
Issue’s Table of Contents
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Published: 29 September 2015
Accepted: 01 May 2015
Revised: 01 May 2015
Received: 01 March 2014
Published in CSUR Volume 48, Issue 1

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  1. Negative bias temperature instability
  2. microprocessor
  3. performance and reliability

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