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A Fault-Aware Toolchain Approach for FPGA Fault Tolerance

Published: 02 March 2015 Publication History

Abstract

As the size and density of silicon chips continue to increase, maintaining acceptable manufacturing yields has become increasingly difficult. Recent works suggest that lithography techniques are reaching their limits with respect to enabling high yield fabrication of small-scale devices, thus there is an increasing need for techniques that can tolerate fabrication time defects. One candidate technology to help combat these defects is reconfigurable hardware. The flexible nature of reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), makes it possible for them to route around defective areas of a chip after the device has been packaged and deployed into the field.
This work presents a technique that aims to increase the effective yield of FPGA manufacturing by re-claiming a portion of chips that would be ordinarily classified as unusable. In brief, we propose a modification to existing commercial toolchain flows to make them fault aware. A phase is added to identify faults within the chip. The locations of these faults are then used by the toolchain to avoid faults during the placement and routing phase.
Specifically, we have applied our approach to the Xilinx commercial toolchain flow and evaluated its tolerance to both logic and routing resource faults. Our findings show that, at a cost of 5--10% in device frequency performance, the modified toolchain flow can tolerate up to 30% of logic resources being faulty and, depending on the nature of the target application, can tolerate 1--30% of the device's routing resources being faulty. These results provide strong evidence that commercial toolchains not designed for the purpose of tolerating faults can still be greatly leveraged in the presence of faults to place and route circuits in an efficient manner.

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  • (2022)A Brief Survey of Fault Tolerant Techniques for Field Programmable Gate Arrays2022 IEEE 12th Annual Computing and Communication Workshop and Conference (CCWC)10.1109/CCWC54503.2022.9720746(0823-0828)Online publication date: 26-Jan-2022
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        cover image ACM Transactions on Design Automation of Electronic Systems
        ACM Transactions on Design Automation of Electronic Systems  Volume 20, Issue 2
        February 2015
        404 pages
        ISSN:1084-4309
        EISSN:1557-7309
        DOI:10.1145/2742143
        • Editor:
        • Naehyuck Chang
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        Published: 02 March 2015
        Accepted: 01 November 2014
        Revised: 01 October 2014
        Received: 01 February 2012
        Published in TODAES Volume 20, Issue 2

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        1. Fault tolerance
        2. design automation
        3. reconfigurable hardware

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        • (2022)A Brief Survey of Fault Tolerant Techniques for Field Programmable Gate Arrays2022 IEEE 12th Annual Computing and Communication Workshop and Conference (CCWC)10.1109/CCWC54503.2022.9720746(0823-0828)Online publication date: 26-Jan-2022
        • (2019)Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologiesJournal of Parallel and Distributed Computing10.1016/j.jpdc.2019.03.021130:C(110-125)Online publication date: 1-Aug-2019
        • (2018)High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2018.60(186-191)Online publication date: Jan-2018
        • (2018)Fast Carry Chain Based Architectures for Two’s Complement to CSD Recoding on FPGAsApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_43(537-550)Online publication date: 8-Apr-2018
        • (2017)Built-In Fault Localization Circuitry for High Performance FPGA Based ImplementationsJournal of Electronic Testing: Theory and Applications10.5555/3128745.312875833:4(529-537)Online publication date: 1-Aug-2017
        • (2017)Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs2017 IEEE 24th International Conference on High Performance Computing (HiPC)10.1109/HiPC.2017.00021(104-113)Online publication date: Dec-2017

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