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Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions

Authors:

Marco Paolieri,

Eduardo Quiñones,

Francisco J. CazorlaAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 12, Issue 1s

Article No.: 64, Pages 1 - 26

https://doi.org/10.1145/2435227.2435260

Published: 29 March 2013 Publication History

Abstract

Multicore processors are an effective solution to cope with the performance requirements of real-time embedded systems due to their good performance-per-watt ratio and high performance capabilities. Unfortunately, their use in integrated architectures such as IMA or AUTOSAR is limited by the fact that multicores do not guarantee a time composable behavior for the applications: the WCET of a task depends on inter-task interferences introduced by other tasks running simultaneously.

This article focuses on the off-chip memory system: the hardware shared resource with the highest impact on the WCET and hence the main impediment for the use of multicores in integrated architectures. We present an analytical model that computes the worst-case delay, also known as Upper Bound Delay (UBD), that a memory request can suffer due to memory interferences generated by other co-running tasks. By considering the UBD in the WCET analysis, the resulting WCET estimation is independent from the other tasks, hence ensuring the time composability property and enabling the use of multicores in integrated architectures. We propose a memory controller for hard real-time multicores compliant with the analytical model that implements extra hardware features to deal with refresh operations and interferences generated by co-running non hard real-time tasks.

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Cited By

Spliet RMullins R(2022)Sim-D: A SIMD Accelerator for Hard Real-Time SystemsIEEE Transactions on Computers10.1109/TC.2021.306429071:4(851-865)Online publication date: 1-Apr-2022
https://doi.org/10.1109/TC.2021.3064290
Hebbache FBrandner FJan MPautet L(2020)Work-conserving dynamic time-division multiplexing for multi-criticality systemsReal-Time Systems10.1007/s11241-019-09336-w56:2(124-170)Online publication date: 1-Apr-2020
https://dl.acm.org/doi/10.1007/s11241-019-09336-w
Dabaghi AFarbeh H(2019)High performance and predictable memory controller for multicore mixed-criticality real-time systemsIET Computers & Digital Techniques10.1049/iet-cdt.2018.5031Online publication date: 12-Jun-2019
https://doi.org/10.1049/iet-cdt.2018.5031
Show More Cited By

Index Terms

Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions
1. Applied computing
  1. Computers in other domains
2. Computer systems organization
  1. Real-time systems

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 12, Issue 1s

Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems

March 2013

701 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2435227

Issue’s Table of Contents

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 29 March 2013

Accepted: 01 May 2012

Revised: 01 March 2012

Received: 01 November 2011

Published in TECS Volume 12, Issue 1s

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Cited By

Spliet RMullins R(2022)Sim-D: A SIMD Accelerator for Hard Real-Time SystemsIEEE Transactions on Computers10.1109/TC.2021.306429071:4(851-865)Online publication date: 1-Apr-2022
https://doi.org/10.1109/TC.2021.3064290
Hebbache FBrandner FJan MPautet L(2020)Work-conserving dynamic time-division multiplexing for multi-criticality systemsReal-Time Systems10.1007/s11241-019-09336-w56:2(124-170)Online publication date: 1-Apr-2020
https://dl.acm.org/doi/10.1007/s11241-019-09336-w
Dabaghi AFarbeh H(2019)High performance and predictable memory controller for multicore mixed-criticality real-time systemsIET Computers & Digital Techniques10.1049/iet-cdt.2018.5031Online publication date: 12-Jun-2019
https://doi.org/10.1049/iet-cdt.2018.5031
Hebbache FJan MBrandner FPautet L(2018)Shedding the Shackles of Time-Division Multiplexing2018 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS.2018.00059(456-468)Online publication date: Dec-2018
https://doi.org/10.1109/RTSS.2018.00059
Doyle NMatthews EHolland GFedorova AShannon L(2017)Performance impacts and limitations of hardware memory access trace collectionProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130496(506-511)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130496
Doyle NMatthews EHolland GFedorova AShannon L(2017)Performance impacts and limitations of hardware memory access trace collectionDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927041(506-511)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927041
Fernandez GJalle JAbella JQuinones EVardanega TCazorla F(2017)Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO ArbitrationIEEE Transactions on Computers10.1109/TC.2016.261630766:4(586-600)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TC.2016.2616307
Gomony MGarside JAkesson BAudsley NGoossens K(2017)A Globally Arbitrated Memory Tree for Mixed-Time-Criticality SystemsIEEE Transactions on Computers10.1109/TC.2016.259558166:2(212-225)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1109/TC.2016.2595581
Samaddar ADas MBanerjee A(2017)A new memory scheduling policy for real time systems2017 7th International Symposium on Embedded Computing and System Design (ISED)10.1109/ISED.2017.8303916(1-4)Online publication date: Dec-2017
https://doi.org/10.1109/ISED.2017.8303916
Kehr SPanić MQuiñones EBöddeker BSandoval JAbella JCazorla FSchäfer GFanucci LTeich J(2016)SupertaskProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971815(25-30)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2971815
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