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Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture

Authors:

Ashwini Sarathy,

Ahmed LouriAuthors Info & Claims

ANCS '07: Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems

Pages 47 - 56

https://doi.org/10.1145/1323548.1323561

Published: 03 December 2007 Publication History

Abstract

Network-on-Chip (NoC)architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the ptimization of NoC architectures has shown that the design of buffers in the NoC routers influences the power consumption, area overhead and performance of the entire network. In this paper, we propose a low-power area-efficient NoC architecture by reducing the number of router buffers. As a reduction in the number of buffers degrades the network's performance, we propose to use the existing repeaters along the inter-router links as adaptive channel buffers for storing data when required. We evaluate the proposed adaptive communication channel buffers under static and dynamic buffer allocation in 8 x 8 mesh and folded torus network topologies. Simulation results show that reducing the router buffer size in half and using the adaptive channel buffers reduces the buffer power by 40-52% and leads to a 17-20% savings in overall network power with a 50% reduction in router area. The design with dynamic buffer allocation shows a marginal 1-5% drop in performance, while static buffer allocation shows a 10-20% drop in performance, for various traffic patterns.

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Cited By

Shpiner AKantor EPu Li Cidon IKeslassy I(2015)On the Capacity of Bufferless Networks-on-ChipIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2014.231022626:2(492-506)Online publication date: 14-Jan-2015
https://dl.acm.org/doi/10.1109/TPDS.2014.2310226
Michelogiannakis GDally W(2013)Elastic Buffer Flow Control for On-Chip NetworksIEEE Transactions on Computers10.1109/TC.2011.23762:2(295-309)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TC.2011.237
Shpiner AKantor ELi PCidon IKeslassy I(2012)On the capacity of bufferless Networks-on-Chip2012 50th Annual Allerton Conference on Communication, Control, and Computing (Allerton)10.1109/Allerton.2012.6483296(770-777)Online publication date: Oct-2012
https://doi.org/10.1109/Allerton.2012.6483296
Show More Cited By

Index Terms

Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture
1. Hardware
  1. Integrated circuits
    1. Interconnect
  2. Very large scale integration design
    1. VLSI system specification and constraints

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Information

Published In

cover image ACM Conferences

ANCS '07: Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems

December 2007

212 pages

ISBN:9781595939456

DOI:10.1145/1323548

General Chair:
Raj Yavatkar
Intel Corporation, USA
,
Program Chairs:
Dirk Grunwald
University of Colorado, USA
,
K. K. Ramakrishnan
AT&T Labs Research, USA

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 03 December 2007

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ANCS07

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ANCS07: Symposium on Architecture for Networking and Communications Systems

December 3 - 4, 2007

Florida, Orlando, USA

Acceptance Rates

ANCS '07 Paper Acceptance Rate 20 of 70 submissions, 29%;

Overall Acceptance Rate 88 of 314 submissions, 28%

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Cited By

Shpiner AKantor EPu Li Cidon IKeslassy I(2015)On the Capacity of Bufferless Networks-on-ChipIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2014.231022626:2(492-506)Online publication date: 14-Jan-2015
https://dl.acm.org/doi/10.1109/TPDS.2014.2310226
Michelogiannakis GDally W(2013)Elastic Buffer Flow Control for On-Chip NetworksIEEE Transactions on Computers10.1109/TC.2011.23762:2(295-309)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TC.2011.237
Shpiner AKantor ELi PCidon IKeslassy I(2012)On the capacity of bufferless Networks-on-Chip2012 50th Annual Allerton Conference on Communication, Control, and Computing (Allerton)10.1109/Allerton.2012.6483296(770-777)Online publication date: Oct-2012
https://doi.org/10.1109/Allerton.2012.6483296
(2011)BibliographyDesigning Network On-Chip Architectures in the Nanoscale Era10.1201/b10477-18(443-475)Online publication date: 9-Feb-2011
https://doi.org/10.1201/b10477-18
Kahng ALin BSamadi KRamanujam RScheffer LPhillips JHu A(2010)Efficient trace-driven metaheuristics for optimization of networks-on-chip configurationsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133485(256-263)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133485
Kahng ALin BSamadi KRamanujam RSapatnekar S(2010)Trace-driven optimization of networks-on-chip configurationsProceedings of the 47th Design Automation Conference10.1145/1837274.1837384(437-442)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837384
Mandal SDenton RMohanty SMahapatra RBahar RLombardi FAtienza DBrunvand E(2010)Low power nanoscale buffer management for network on chip routersProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785540(245-250)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785540
Kahng ALin BSamadi KRamanujam R(2010)Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2010.5654164(256-263)Online publication date: Nov-2010
https://doi.org/10.1109/ICCAD.2010.5654164
Michelogiannakis GDally WPinfold W(2009)Router designs for elastic buffer on-chip networksProceedings of the Conference on High Performance Computing Networking, Storage and Analysis10.1145/1654059.1654062(1-10)Online publication date: 14-Nov-2009
https://dl.acm.org/doi/10.1145/1654059.1654062
Wang LZhang JYang XWen DLombardi FBhanja SMassoud YBahar R(2009)Router with centralized buffer for network-on-chipProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531649(469-474)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531649
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