Article

Cache Array Architecture Optimization at Deep Submicron Technologies

Authors:

Annie Y. Zeng,

Ken Rose,

Ronald J. GutmannAuthors Info & Claims

ICCD '04: Proceedings of the IEEE International Conference on Computer Design

Pages 320 - 325

Published: 11 October 2004 Publication History

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Abstract

A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and cycle times of on-chip memory using circuit models based on Cadence simulations. Lumped RC models have been used to approximate the distributed RC interconnect network in the access time models. Both SRAM and DRAM models have been validated with industrial designs. The limited influences of gate fan-out and transistor size on the cache array architecture indicate that interconnect delay is dominant at deep submicron technologies.

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Kodi AMorris ROnufryk PRamakrishnan KCrowley PWroclawski J(2009)Design of a scalable nanophotonic interconnect for future multicoresProceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems10.1145/1882486.1882516(113-122)Online publication date: 19-Oct-2009
https://dl.acm.org/doi/10.1145/1882486.1882516
Kodi ASarathy ALouri AYavatkar RGrunwald DRamakrishnan K(2007)Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architectureProceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems10.1145/1323548.1323561(47-56)Online publication date: 3-Dec-2007
https://dl.acm.org/doi/10.1145/1323548.1323561
Zeng ALu JRose KGutmann R(2005)First-Order Performance Prediction of Cache Memory with Wafer-Level3D IntegrationIEEE Design & Test10.1109/MDT.2005.13822:6(548-555)Online publication date: 1-Nov-2005
https://dl.acm.org/doi/10.1109/MDT.2005.138

Cache Array Architecture Optimization at Deep Submicron Technologies
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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ICCD '04: Proceedings of the IEEE International Conference on Computer Design

October 2004

537 pages

ISBN:0769522319

Publisher

IEEE Computer Society

United States

Publication History

Published: 11 October 2004

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Kodi AMorris ROnufryk PRamakrishnan KCrowley PWroclawski J(2009)Design of a scalable nanophotonic interconnect for future multicoresProceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems10.1145/1882486.1882516(113-122)Online publication date: 19-Oct-2009
https://dl.acm.org/doi/10.1145/1882486.1882516
Kodi ASarathy ALouri AYavatkar RGrunwald DRamakrishnan K(2007)Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architectureProceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems10.1145/1323548.1323561(47-56)Online publication date: 3-Dec-2007
https://dl.acm.org/doi/10.1145/1323548.1323561
Zeng ALu JRose KGutmann R(2005)First-Order Performance Prediction of Cache Memory with Wafer-Level3D IntegrationIEEE Design & Test10.1109/MDT.2005.13822:6(548-555)Online publication date: 1-Nov-2005
https://dl.acm.org/doi/10.1109/MDT.2005.138

Abstract

Cited By

Recommendations

Reducing leakage in a high-performance deep-submicron instruction cache

An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches

Intrinsic leakage in deep submicron CMOS ICs—measurement-based test solutions

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