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Article

Enforcing isolation and ordering in STM

Authors:

Tatiana Shpeisman,

Ali-Reza Adl-Tabatabai,

Steven Balensiefer,

Richard L. Hudson,

Katherine F. Moore,

Bratin SahaAuthors Info & Claims

PLDI '07: Proceedings of the 28th ACM SIGPLAN Conference on Programming Language Design and Implementation

Pages 78 - 88

https://doi.org/10.1145/1250734.1250744

Published: 10 June 2007 Publication History

Abstract

Transactional memory provides a new concurrency control mechanism that avoids many of the pitfalls of lock-based synchronization. High-performance software transactional memory (STM) implementations thus far provide weak atomicity: Accessing shared data both inside and outside a transaction can result in unexpected, implementation-dependent behavior. To guarantee isolation and consistent ordering in such a system, programmers are expected to enclose all shared-memory accesses inside transactions.

A system that provides strong atomicity guarantees isolation even in the presence of threads that access shared data outside transactions. A strongly-atomic system also orders transactions with conflicting non-transactional memory operations in a consistent manner.

In this paper, we discuss some surprising pitfalls of weak atomicity, and we present an STM system that avoids these problems via strong atomicity. We demonstrate how to implement non-transactional data accesses via efficient read and write barriers, and we present compiler optimizations that further reduce the overheads of these barriers. We introduce a dynamic escape analysis that differentiates private and public data at runtime to make barriers cheaper and a static not-accessed-in-transaction analysis that removes many barriers completely. Our results on a set of Java programs show that strong atomicity can be implemented efficiently in a high-performance STM system.

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Cited By

Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071113
Li ZLiu LDeng YWang JLiu ZYin SWei S(2019)FPGA-Accelerated Optimistic Concurrency Control for Transactional MemoryProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358270(911-923)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358270
Dongol BJagadeesan RRiely JHollingsworth JKeidar I(2019)Modular transactionsProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295708(82-93)Online publication date: 16-Feb-2019
https://dl.acm.org/doi/10.1145/3293883.3295708
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Index Terms

Enforcing isolation and ordering in STM
1. Computing methodologies
  1. Parallel computing methodologies
    1. Parallel programming languages
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Runtime environments
      2. Source code generation
    2. General programming languages
      1. Language features
        Concurrent programming structures
      2. Language types
        Parallel programming languages

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Published In

cover image ACM Conferences

PLDI '07: Proceedings of the 28th ACM SIGPLAN Conference on Programming Language Design and Implementation

June 2007

508 pages

ISBN:9781595936332

DOI:10.1145/1250734

General Chair:
Jeanne Ferrante
University of California, San Diego, USA
,
Program Chair:
Kathryn S. McKinley
University of Texas at Austin, USA

ACM SIGPLAN Notices Volume 42, Issue 6
Proceedings of the 2007 PLDI conference
June 2007
491 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1273442
Issue’s Table of Contents

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 June 2007

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PLDI '07: ACM SIGPLAN Conference on Programming Language Design and Implementation

June 10 - 13, 2007

California, San Diego, USA

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Cited By

Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071113
Li ZLiu LDeng YWang JLiu ZYin SWei S(2019)FPGA-Accelerated Optimistic Concurrency Control for Transactional MemoryProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358270(911-923)Online publication date: 12-Oct-2019
https://dl.acm.org/doi/10.1145/3352460.3358270
Dongol BJagadeesan RRiely JHollingsworth JKeidar I(2019)Modular transactionsProceedings of the 24th Symposium on Principles and Practice of Parallel Programming10.1145/3293883.3295708(82-93)Online publication date: 16-Feb-2019
https://dl.acm.org/doi/10.1145/3293883.3295708
Sotiropolos PVassilakis C(2019)Detection of intermittent faults in software programs through identification of suspicious shared variable access patternsJournal of Systems and Software10.1016/j.jss.2019.110455(110455)Online publication date: Oct-2019
https://doi.org/10.1016/j.jss.2019.110455
Chong NSorensen TWickerson J(2018)The semantics of transactions and weak memory in x86, Power, ARM, and C++ACM SIGPLAN Notices10.1145/3296979.319237353:4(211-225)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3296979.3192373
Chong NSorensen TWickerson JFoster JGrossman D(2018)The semantics of transactions and weak memory in x86, Power, ARM, and C++Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3192366.3192373(211-225)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3192366.3192373
Kanrar S(2018)SME: A New Software Transactional Memory Based Mutual Exclusion Algorithm for Distributed SystemsComputer Information Systems and Industrial Management10.1007/978-3-319-99954-8_30(354-369)Online publication date: 5-Sep-2018
https://doi.org/10.1007/978-3-319-99954-8_30
Sengupta ACao MBond MKulkarni MReddi VSmith ATang L(2017)Legato: end-to-end bounded region serializability using commodity hardware transactional memoryProceedings of the 2017 International Symposium on Code Generation and Optimization10.5555/3049832.3049834(1-13)Online publication date: 4-Feb-2017
https://dl.acm.org/doi/10.5555/3049832.3049834
Wood BCao MBond MGrossman D(2017)Instrumentation bias for dynamic data race detectionProceedings of the ACM on Programming Languages10.1145/31338931:OOPSLA(1-31)Online publication date: 12-Oct-2017
https://dl.acm.org/doi/10.1145/3133893
Zhou TLuchangco VSpear MScheideler CHajiaghayi M(2017)Hand-Over-Hand Transactions with Precise Memory ReclamationProceedings of the 29th ACM Symposium on Parallelism in Algorithms and Architectures10.1145/3087556.3087587(255-264)Online publication date: 24-Jul-2017
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