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Performance from architecture: comparing a RISC and a CISC with similar hardware organization

Authors:

Dileep Bhandarkar,

Douglas W. ClarkAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 19, Issue 2

Pages 310 - 319

https://doi.org/10.1145/106975.107003

Published: 01 April 1991 Publication History

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Cited By

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Narnolia VJana USaha T(2020)Multi-Arc Processor—Harnessing Pseudo-concurrent Multiple Instruction Set Architecture (ISA) Over a Single Hardware PlatformProceedings of the Global AI Congress 201910.1007/978-981-15-2188-1_42(535-548)Online publication date: 3-Apr-2020
https://doi.org/10.1007/978-981-15-2188-1_42
Han SJiang Y(2023)RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.326810831:7(980-992)Online publication date: Jul-2023
https://doi.org/10.1109/TVLSI.2023.3268108
Yun JRustamov FKim JShin Y(2022)Fuzzing of Embedded Systems: A SurveyACM Computing Surveys10.1145/353864455:7(1-33)Online publication date: 15-Dec-2022
https://dl.acm.org/doi/10.1145/3538644
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Index Terms

Performance from architecture: comparing a RISC and a CISC with similar hardware organization
1. Computer systems organization
  1. Architectures
    1. Serial architectures
2. General and reference
  1. Cross-computing tools and techniques
    1. Performance

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 19, Issue 2

Apr. 1991

305 pages

ISSN:0163-5964

DOI:10.1145/106975

Editor:
David A. Patterson
Univ. of California, Berkeley

Issue’s Table of Contents

ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
April 1991
320 pages
ISBN:0897913809
DOI:10.1145/106972
Chairman:
David A. Patterson
Univ. of California, Berkeley
,
General Chair:
Bob Rau

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1991

Published in SIGARCH Volume 19, Issue 2

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Cited By

View all

Narnolia VJana USaha T(2020)Multi-Arc Processor—Harnessing Pseudo-concurrent Multiple Instruction Set Architecture (ISA) Over a Single Hardware PlatformProceedings of the Global AI Congress 201910.1007/978-981-15-2188-1_42(535-548)Online publication date: 3-Apr-2020
https://doi.org/10.1007/978-981-15-2188-1_42
Han SJiang Y(2023)RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.326810831:7(980-992)Online publication date: Jul-2023
https://doi.org/10.1109/TVLSI.2023.3268108
Yun JRustamov FKim JShin Y(2022)Fuzzing of Embedded Systems: A SurveyACM Computing Surveys10.1145/353864455:7(1-33)Online publication date: 15-Dec-2022
https://dl.acm.org/doi/10.1145/3538644
Huybrechts TMercelis SHellinckx P(2020)A Survey on the Software and Hardware-Based Influences on the Worst-Case Execution TimeAdvances on P2P, Parallel, Grid, Cloud and Internet Computing10.1007/978-3-030-61105-7_27(271-281)Online publication date: 9-Oct-2020
https://doi.org/10.1007/978-3-030-61105-7_27
Hennessy JPatterson D(2019)A new golden age for computer architectureCommunications of the ACM10.1145/328230762:2(48-60)Online publication date: 28-Jan-2019
https://dl.acm.org/doi/10.1145/3282307
Patterson D(2018)50 Years of computer architecture: From the mainframe CPU to the domain-specific tpu and the open RISC-V instruction set2018 IEEE International Solid - State Circuits Conference - (ISSCC)10.1109/ISSCC.2018.8310168(27-31)Online publication date: Feb-2018
https://doi.org/10.1109/ISSCC.2018.8310168
Uddin I(2017)One-IPC high-level simulation of microthreaded many-core architecturesInternational Journal of High Performance Computing Applications10.1177/109434201558449531:2(152-162)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1177/1094342015584495
Patterson D(2017)Reduced Instruction Set Computers Then and NowComputer10.1109/MC.2017.445120650:12(10-12)Online publication date: 1-Dec-2017
https://dl.acm.org/doi/10.1109/MC.2017.4451206
Blem EMenon JVijayaraghavan TSankaralingam K(2015)ISA WarsACM Transactions on Computer Systems10.1145/269968233:1(1-34)Online publication date: 11-Mar-2015
https://dl.acm.org/doi/10.1145/2699682
Tomar GVerma S(2009)Dynamic Multi-level Hierarchal Clustering Approach for Wireless Sensor NetworksProceedings of the UKSim 2009: 11th International Conference on Computer Modelling and Simulation10.1109/UKSIM.2009.84(563-567)Online publication date: 25-Mar-2009
https://dl.acm.org/doi/10.1109/UKSIM.2009.84
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